Sergei Shtylyov <[email protected]> writes: > On 10/2/2015 5:26 PM, Måns Rullgård wrote: > >>>> Some SoCs have a UART with a non-standard register layout. This >>>> allows the debug console to work with these. >>> >>>> Signed-off-by: Mans Rullgard <[email protected]> >>>> --- >>>> I would have preferred a more accurate description of the UART, but I've >>>> not managed to figure out who the vendor is. >>> >>> You haven't seem the Alchemy datasheets? I can send you some if so. >> >> I have. They don't say where Alchemy bought the UART block. > > In fact, seeing at least Au1550 databook googling for "alchemy databook". > The UART registers are described there. Perhaps, it's not accurate > enought for your needs, though...
I have all the information I need about how it works. >>>> --- >>>> arch/arm/Kconfig.debug | 4 ++++ >>>> arch/arm/include/debug/8250.S | 12 ++++++++++++ >>>> 2 files changed, 16 insertions(+) >>>> >>>> diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug >>>> index 0cfd7f9..8d5c837 100644 >>>> --- a/arch/arm/Kconfig.debug >>>> +++ b/arch/arm/Kconfig.debug >>>> @@ -1597,6 +1597,10 @@ config DEBUG_UART_8250_WORD >>>> DEBUG_BCM_KONA_UART || DEBUG_RK32_UART2 || \ >>>> DEBUG_BRCMSTB_UART >>>> >>>> +config DEBUG_UART_8250_AU >>>> + bool "8250 UART has Alchemy register layout" >>>> + depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250 >>>> + >>> >>> So Alchemy UART got reused on ARM? >> >> The UART is actually a Palmchip IP core used by several SoC companies. > > Hm, how have you figured out that;s Palmchip if the Alchemy > databooks are silent about that? :-) Someone with access to hardware design files told me. -- Måns Rullgård [email protected] -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
