The D1/D1s SoCs support xtheadvector which should be included in the devicetree. Also include vendorid and archid for the cpu.
Signed-off-by: Charlie Jenkins <[email protected]> --- arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi index 64c3c2e6cbe0..aee07d33a4d3 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi @@ -27,7 +27,9 @@ cpu0: cpu@0 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + "zifencei", "zihpm", "xtheadvector"; + riscv,vendorid = <0x00000000 0x0000005b7>; + riscv,archid = <0x00000000 0x000000000>; #cooling-cells = <2>; cpu0_intc: interrupt-controller { -- 2.44.0
