On Fri, Apr 12, 2024 at 02:49:00PM +0800, Andy Chiu wrote: > Multiple Vector subextensions are added. Also, the patch takes care of > the dependencies of Vector subextensions by macro expansions. So, if > some "embedded" platform only reports "zve64f" on the ISA string, the > parser is able to expand it to zve32x zve32f zve64x and zve64f. > > Signed-off-by: Andy Chiu <[email protected]> > --- > Changelog v3: > - renumber RISCV_ISA_EXT_ZVE* to rebase on top of 6.9 > - alphabetically sort added extensions (Clément) > Changelog v2: > - remove the extension itself from its isa_exts[] list (Clément) > - use riscv_zve64d_exts for v's extension list (Samuel) > --- > arch/riscv/include/asm/hwcap.h | 5 +++++ > arch/riscv/kernel/cpufeature.c | 36 +++++++++++++++++++++++++++++++++++- > 2 files changed, 40 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index e17d0078a651..f64d4e98e67c 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -81,6 +81,11 @@ > #define RISCV_ISA_EXT_ZTSO 72 > #define RISCV_ISA_EXT_ZACAS 73 > #define RISCV_ISA_EXT_XANDESPMU 74 > +#define RISCV_ISA_EXT_ZVE32X 75 > +#define RISCV_ISA_EXT_ZVE32F 76 > +#define RISCV_ISA_EXT_ZVE64X 77 > +#define RISCV_ISA_EXT_ZVE64F 78 > +#define RISCV_ISA_EXT_ZVE64D 79 > > #define RISCV_ISA_EXT_XLINUXENVCFG 127 > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index f6f3ece60d69..38d09de518b1 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -188,6 +188,35 @@ static const unsigned int riscv_zvbb_exts[] = { > RISCV_ISA_EXT_ZVKB > }; > > +#define RISCV_ISA_EXT_ZVE32F_IMPLY_LIST \ > + RISCV_ISA_EXT_ZVE32X,
Not really a reason to have a list here, there's only one thing implied. Otherwise, Reviewed-by: Conor Dooley <[email protected]> Cheers, Conor.
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