On Mon, Jun 10, 2024 at 03:56:40PM -0700, Charlie Jenkins wrote: > The D1/D1s SoCs support xtheadvector so it can be included in the > devicetree. Also include vlenb for the cpu. > > Signed-off-by: Charlie Jenkins <[email protected]>
Reviewed-by: Conor Dooley <[email protected]> > --- > arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > index 64c3c2e6cbe0..6367112e614a 100644 > --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > @@ -27,7 +27,8 @@ cpu0: cpu@0 { > riscv,isa = "rv64imafdc"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", > - "zifencei", "zihpm"; > + "zifencei", "zihpm", > "xtheadvector"; > + thead,vlenb = <128>; > #cooling-cells = <2>; > > cpu0_intc: interrupt-controller { > > -- > 2.44.0 >
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