> diff --git a/arch/loongarch/include/asm/inst.h
> b/arch/loongarch/include/asm/inst.h
> index 76b723590023..636cfc524b02 100644
> --- a/arch/loongarch/include/asm/inst.h
> +++ b/arch/loongarch/include/asm/inst.h
> @@ -783,6 +783,8 @@ DEF_EMIT_REG3_FORMAT(amswapb, amswapb_op)
> DEF_EMIT_REG3_FORMAT(amswaph, amswaph_op)
> DEF_EMIT_REG3_FORMAT(amswapw, amswapw_op)
> DEF_EMIT_REG3_FORMAT(amswapd, amswapd_op)
> +DEF_EMIT_REG3_FORMAT(amswapdbw, amswapdbw_op)
> +DEF_EMIT_REG3_FORMAT(amswapdbd, amswapdbd_op)
>
> #define DEF_EMIT_REG3SA2_FORMAT(NAME, OP) \
> static inline void emit_##NAME(union loongarch_instruction *insn, \
[ ... ]
> diff --git a/arch/loongarch/net/bpf_jit.c b/arch/loongarch/net/bpf_jit.c
> index 24913dc7f4e8..b2bc54b4ca87 100644
> --- a/arch/loongarch/net/bpf_jit.c
> +++ b/arch/loongarch/net/bpf_jit.c
> @@ -486,7 +486,7 @@ static int emit_atomic_rmw(const struct bpf_insn *insn,
> struct jit_ctx *ctx)
> emit_zext_32(ctx, src, true);
> break;
> case BPF_DW:
> - emit_insn(ctx, amswapd, src, t1, t3);
> + emit_insn(ctx, amswapdbd, src, t1, t3);
> break;
> }
> break;
The patch defines amswapdbw in asm/inst.h to provide the ordered 32-bit
exchange instruction, but does the BPF_W case of BPF_XCHG in
emit_atomic_rmw() also need to be updated?
Currently, the 32-bit exchange uses the weakly ordered amswapw instruction
at the BPF_W case:
arch/loongarch/net/bpf_jit.c:emit_atomic_rmw() {
...
case BPF_W:
emit_insn(ctx, amswapw, src, t1, t3);
emit_zext_32(ctx, src, true);
...
}
Should this be updated to use the new amswapdbw instruction to ensure the
BPF memory ordering guarantees are met for 32-bit exchanges?
Reference:
https://lore.kernel.org/bpf/[email protected]/
[ ... ]
---
AI reviewed your patch. Please fix the bug or email reply why it's not a bug.
See: https://github.com/kernel-patches/vmtest/blob/master/ci/claude/README.md
CI run summary: https://github.com/kernel-patches/bpf/actions/runs/26794506560
