> diff --git a/arch/loongarch/net/bpf_jit.c b/arch/loongarch/net/bpf_jit.c
> index f071d913e054..4f3aa53eda20 100644
> --- a/arch/loongarch/net/bpf_jit.c
> +++ b/arch/loongarch/net/bpf_jit.c
> @@ -2362,6 +2362,11 @@ bool bpf_jit_supports_fsession(void)
> return true;
> }
>
> +bool bpf_jit_supports_ptr_xchg(void)
> +{
> + return true;
> +}
> +
While patch 1 fixed BPF_XCHG (32/64-bit) to use amswap_db.{w,d} for full
barriers, do the other value-returning atomic RMW instructions also need
updates to ensure sequential consistency?
According to the Linux Kernel Memory Model, value-returning atomic RMW
instructions must be fully ordered. In emit_atomic_rmw():
1. BPF_FETCH operations (BPF_ADD|BPF_FETCH, BPF_AND|BPF_FETCH, etc.) use
plain amadd.{b,h,w,d}, amand.{w,d}, amor.{w,d}, amxor.{w,d} without _db
variants
2. Sub-word BPF_XCHG (BPF_B, BPF_H) use plain amswap.{b,h} without barriers
3. BPF_CMPXCHG uses bare ll/sc loops without dbar instructions
Could this leave BPF programs vulnerable to memory reordering bugs on
LoongArch if dbar 0 is not emitted or if the _db variants are not used?
(This was raised by [email protected] in v2:
https://lore.kernel.org/bpf/[email protected]/)
> /* Indicate the JIT backend supports mixing bpf2bpf and tailcalls. */
> bool bpf_jit_supports_subprog_tailcalls(void)
> {
---
AI reviewed your patch. Please fix the bug or email reply why it's not a bug.
See: https://github.com/kernel-patches/vmtest/blob/master/ci/claude/README.md
CI run summary: https://github.com/kernel-patches/bpf/actions/runs/26878707871
