On Wednesday 21 May 2014 11:39:07 pm Geert Uytterhoeven wrote:
> On Thu, May 22, 2014 at 1:00 AM,  <[email protected]> wrote:
> > +#define MCFGPIO_PODR           (MCF_MBAR + 0xA00)
> > +#define MCFGPIO_PDDR           (MCF_MBAR + 0xA10)
> > +#define MCFGPIO_PPDR           (MCF_MBAR + 0xA20)
> > +#define MCFGPIO_SETR           (MCF_MBAR + 0xA20)
> 
> The above two are identical. Is that intentional?

Yes.  Functionally, the PPDRs are read-only registers that when read, return 
the current state of the pins and the SETRs are write-only registers that for 
each pin configured as an output, if the corresponding bit in the write is a 1, 
the pin is driven high, and if the bit is 0, no effect.
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