Signed-off-by: Yannick GICQUEL <[email protected]>
---
arch/m68k/include/asm/m54xxacr.h | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h
index 6d13cae..e79f48e 100644
--- a/arch/m68k/include/asm/m54xxacr.h
+++ b/arch/m68k/include/asm/m54xxacr.h
@@ -94,8 +94,20 @@
* register region as non-cacheable. And then we map all our RAM as
* cacheable and supervisor access only.
*/
+#ifdef CONFIG_M5441x
+/*
+ * MBAR register is not present in this serie
+ * Periph #0 in 0xe0000000--0x0xefffffff
+ * Periph #1 in 0xf0000000--0x0xffffffff
+ *
+ * Let's hardcode these values for ACR0
+ */
+#define ACR0_MODE (ACR_BA(0xE0000000)+ACR_ADMSK(0x20000000)+ \
+ ACR_ENABLE+ACR_SUPER+ACR_CM_OFF_PRE+ACR_SP)
+#else
#define ACR0_MODE (ACR_BA(CONFIG_MBAR)+ACR_ADMSK(0x1000000)+ \
ACR_ENABLE+ACR_SUPER+ACR_CM_OFF_PRE+ACR_SP)
+#endif
#if defined(CONFIG_CACHE_COPYBACK)
#define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \
ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_CP)
@@ -106,7 +118,6 @@
#define ACR2_MODE 0
#define ACR3_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \
ACR_ENABLE+ACR_SUPER+ACR_SP)
-
#else
/*
--
1.9.1.286.g5172cb3
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