Hi Kieran,
Thank you for the patch.
On Friday, 11 January 2019 19:41:40 EET Kieran Bingham wrote:
> The ADV748x is currently reset by writting a small table of registers to
> the device.
>
> The table lacks documentation and contains magic values to perform the
> actions, including using a fake register address to introduce a delay
> loop.
>
> Remove the table, and convert to code, documenting the purpose of the
> specific writes along the way.
>
> Signed-off-by: Kieran Bingham <kieran.bingham+rene...@ideasonboard.com>
> ---
> drivers/media/i2c/adv748x/adv748x-core.c | 32 ++++++++++++++++--------
> drivers/media/i2c/adv748x/adv748x.h | 16 ++++++++++++
> 2 files changed, 38 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/media/i2c/adv748x/adv748x-core.c
> b/drivers/media/i2c/adv748x/adv748x-core.c index 02f9c440301c..252bdb28b18b
> 100644
> --- a/drivers/media/i2c/adv748x/adv748x-core.c
> +++ b/drivers/media/i2c/adv748x/adv748x-core.c
> @@ -389,15 +389,6 @@ static const struct media_entity_operations
> adv748x_media_ops = { * HW setup
> */
>
> -static const struct adv748x_reg_value adv748x_sw_reset[] = {
> -
> - {ADV748X_PAGE_IO, 0xff, 0xff}, /* SW reset */
> - {ADV748X_PAGE_WAIT, 0x00, 0x05},/* delay 5 */
> - {ADV748X_PAGE_IO, 0x01, 0x76}, /* ADI Required Write */
> - {ADV748X_PAGE_IO, 0xf2, 0x01}, /* Enable I2C Read Auto-Increment */
> - {ADV748X_PAGE_EOR, 0xff, 0xff} /* End of register table */
> -};
> -
> /* Initialize CP Core with RGB888 format. */
> static const struct adv748x_reg_value adv748x_init_hdmi[] = {
> /* Disable chip powerdown & Enable HDMI Rx block */
> @@ -474,12 +465,33 @@ static const struct adv748x_reg_value
> adv748x_init_afe[] = { {ADV748X_PAGE_EOR, 0xff, 0xff} /* End of register
> table */
> };
>
> +static int adv748x_sw_reset(struct adv748x_state *state)
> +{
> + int ret;
> +
> + ret = io_write(state, ADV748X_IO_REG_FF, ADV748X_IO_REG_FF_MAIN_RESET);
> + if (ret)
> + return ret;
> +
> + usleep_range(5000, 6000);
> +
> + /* Disable CEC Wakeup from power-down mode */
> + ret = io_clrset(state, ADV748X_IO_REG_01, ADV748X_IO_REG_01_PWRDN_MASK,
> + ADV748X_IO_REG_01_PWRDNB);
What's the reason for io_clrset() instead of io_write() ?
Apart from this,
Reviewed-by: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
> + if (ret)
> + return ret;
> +
> + /* Enable I2C Read Auto-Increment for consecutive reads */
> + return io_write(state, ADV748X_IO_REG_F2,
> + ADV748X_IO_REG_F2_READ_AUTO_INC);
> +}
> +
> static int adv748x_reset(struct adv748x_state *state)
> {
> int ret;
> u8 regval = 0;
>
> - ret = adv748x_write_regs(state, adv748x_sw_reset);
> + ret = adv748x_sw_reset(state);
> if (ret < 0)
> return ret;
>
> diff --git a/drivers/media/i2c/adv748x/adv748x.h
> b/drivers/media/i2c/adv748x/adv748x.h index b00c1995efb0..2f8d751cfbb0
> 100644
> --- a/drivers/media/i2c/adv748x/adv748x.h
> +++ b/drivers/media/i2c/adv748x/adv748x.h
> @@ -211,6 +211,11 @@ struct adv748x_state {
> #define ADV748X_IO_PD 0x00 /* power down controls
> */
> #define ADV748X_IO_PD_RX_EN BIT(6)
>
> +#define ADV748X_IO_REG_01 0x01 /* pwrdn{2}b, prog_xtal_freq */
> +#define ADV748X_IO_REG_01_PWRDN_MASK (BIT(7) | BIT(6))
> +#define ADV748X_IO_REG_01_PWRDN2B BIT(7) /* CEC Wakeup Support */
> +#define ADV748X_IO_REG_01_PWRDNB BIT(6) /* CEC Wakeup Support */
> +
> #define ADV748X_IO_REG_04 0x04
> #define ADV748X_IO_REG_04_FORCE_FR BIT(0) /* Force CP free-run */
>
> @@ -229,8 +234,19 @@ struct adv748x_state {
> #define ADV748X_IO_CHIP_REV_ID_1 0xdf
> #define ADV748X_IO_CHIP_REV_ID_2 0xe0
>
> +#define ADV748X_IO_REG_F2 0xf2
> +#define ADV748X_IO_REG_F2_READ_AUTO_INC BIT(0)
> +
> +/* For PAGE slave address offsets */
> #define ADV748X_IO_SLAVE_ADDR_BASE 0xf2
>
> +/*
> + * The ADV748x_Recommended_Settings_PrA_2014-08-20.pdf details both 0x80
> and + * 0xff as examples for performing a software reset.
> + */
> +#define ADV748X_IO_REG_FF 0xff
> +#define ADV748X_IO_REG_FF_MAIN_RESET 0xff
> +
> /* HDMI RX Map */
> #define ADV748X_HDMI_LW1 0x07 /* line width_1 */
> #define ADV748X_HDMI_LW1_VERT_FILTER BIT(7)
--
Regards,
Laurent Pinchart
