On i.MX8MQ/MM a separate control block contains registers for per-core
resets, clock gating, and fuse register control.
Signed-off-by: Philipp Zabel <p.za...@pengutronix.de>
Reviewed-by: Boris Brezillon <boris.brezil...@collabora.com>
---
drivers/staging/media/hantro/hantro.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/staging/media/hantro/hantro.h
b/drivers/staging/media/hantro/hantro.h
index e8eb747f22ef..5c2f87272ce2 100644
--- a/drivers/staging/media/hantro/hantro.h
+++ b/drivers/staging/media/hantro/hantro.h
@@ -167,6 +167,7 @@ hantro_vdev_to_func(struct video_device *vdev)
* @reg_bases: Mapped addresses of VPU registers.
* @enc_base: Mapped address of VPU encoder register for convenience.
* @dec_base: Mapped address of VPU decoder register for convenience.
+ * @ctrl_base: Mapped address of VPU control block.
* @vpu_mutex: Mutex to synchronize V4L2 calls.
* @irqlock: Spinlock to synchronize access to data structures
* shared with interrupt handlers.
@@ -185,6 +186,7 @@ struct hantro_dev {
void __iomem **reg_bases;
void __iomem *enc_base;
void __iomem *dec_base;
+ void __iomem *ctrl_base;
struct mutex vpu_mutex; /* video_device lock */
spinlock_t irqlock;
--
2.20.1
