On Wed, 11 Sep 2019, at 04:37, Jae Hyun Yoo wrote: > This commit refines hsync/vsync polarity setting logic by making > also clearing register bits possible based on probed sync state > accordingly. That was tough to parse, but I think I understand. Trying to rephrase: Enable clearing of hsync/vsync plarity bits based on probed sync state. What was the issue that drove the change? Do you know why it was done the way it was prior to this patch? Andrew
- [PATCH -next 0/2] media: aspeed: refine mode detection flow Jae Hyun Yoo
- [PATCH -next 1/2] media: aspeed: refine hsync/vsync po... Jae Hyun Yoo
- Re: [PATCH -next 1/2] media: aspeed: refine hsync/... Andrew Jeffery
- Re: [PATCH -next 1/2] media: aspeed: refine hs... Jae Hyun Yoo
- [PATCH -next 2/2] media: aspeed: set hsync and vsync p... Jae Hyun Yoo
- Re: [PATCH -next 2/2] media: aspeed: set hsync and... Andrew Jeffery
- Re: [PATCH -next 2/2] media: aspeed: set hsync... Jae Hyun Yoo
- Re: [PATCH -next 2/2] media: aspeed: set h... Andrew Jeffery
- Re: [PATCH -next 2/2] media: aspeed: ... Jae Hyun Yoo