Am Freitag, 21. November 2014, 10:06:47 schrieb James Hogan:
> On Thu, Nov 20, 2014 at 01:56:24PM +0100, Heiko Stübner wrote:
> > I don't know enough about your clock structure, but it looks quite a bit
> > like Mike's mail from May [0] may apply here too.
> > 
> > The register layout also suggests that it is indeed one clock ip-block:
> > 
> > 0x02005908 0x4      CR_TOP_CLKSWITCH
> > 0x0200590c 0x4      CR_TOP_CLKENAB
> > 0x02005950 0x4      CR_TOP_SYSPLL_CTL0
> > 0x02005954 0x4      CR_TOP_SYSPLL_CTL1
> > 0x02005988 0x4      CR_TOP_CLKSWITCH2
> > 0x0200598c 0x4      CR_TOP_CLKENAB2
> > ...
> > 
> > 
> > [0]
> Thanks, that does make sense. It's probably more like 4 memory regions
> ("top" level, "perip" peripheral registers, "hep" high end peripheral
> registers, and "pdc" powerdown controller registers), but it could
> certainly still have a single binding with multiple memory regions to
> simplify the clock specifiers.

It could also make sense to have 4 clock controller nodes for those. I guess 
it all depends on how the hardware is layed out.

For example on Rockchip SoCs, all of this is contained in the "APB CRU" (Clock 
and Reset Unit) with a memory region of <0x20000000 0x4000> - so here one 
hardware-block that contains all the clocks and also the reset controller.

On the other hand it might very well be more than one ip-block on your 

So I guess it comes down to looking at the memory map [or documentation :-) ] 
to determine how many ip blocks there really are.

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