Chris Johnson writes:
>
> Unless I'm missing something, virtually indexed/physically
> tagged is not sufficient. You also need cache tag snooping
> logic to detect updates at misaligned virtual aliases.
>
> This is pretty easy to deal with in s/w. I think it is only
> worthwhile in h/w if you add DMA cache coherence, which can
> fall out of the snooping logic pretty easily - again given
> sufficient h/w development resources.
Low-end processors, such as the QED processors, do not have
snooping (for I/O or for aliased tags), mostly for cost and
performance reasons.
Without the hardware, the software either has to avoid aliases
(as by using a larger page size: 16 KB will do the trick on an R5000,
or by choosing mapping addresses carefully), or has to do ownership
switching of aliases via the TLB. IRIX both chooses addresses carefully
and does ownership switching.
