Barry Song <[email protected]> on behalf of Shi bin <[email protected]>
>
>
Hi, list,
I’m new to here for investigating sd/mmc driver in our Cortex-A9
Single core platform board. Our sd/mmc host controller is fully
compatible with standard SD specification 2.0 but one specific
feature: slot 0 and slot 2 shared 8 bits data pins, which means at one
time, only one slot could be accessed through 8 bits data pins with a
switch defined in controller register.
I have researched in SDHCI driver in Linux kernel and don’t find any
codes dealing with the feature I mentioned, right? What I consider
about is, high layer send r/w request to mmc core, and sdhci_request
in lower driver be fired, I just add logic about switch 8 bits data
pins here. Other defined functions or callbacks seems could not
handler this thing, eg platform_8bit_width() and
platform_send_init_74_clocks(). Our sd/mmc host controller driver is a
wrapper on standard SDHCI driver.
So, all in all, I apply additional new quirks(occupy last bit 31) and
sdhci_ops callback shared_data_bus as below.
Index: include/linux/mmc/sdhci.h
===================================================================
--- include/linux/mmc/sdhci.h (revision 4482)
+++ include/linux/mmc/sdhci.h (working copy)
@@ -85,8 +85,6 @@
#define SDHCI_QUIRK_NO_HISPD_BIT
(1<<29)
/* Controller treats ADMA descriptors with length 0000h incorrectly */
#define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30)
+/* Controller share 8 bits data pins */
+#define SDHCI_QUIRK_SHARE_DATA_PINS
(1<<31)
int irq; /* Device IRQ */
void __iomem *ioaddr; /* Mapped address */
Index: drivers/mmc/host/sdhci.h
===================================================================
--- drivers/mmc/host/sdhci.h (revision 4481)
+++ drivers/mmc/host/sdhci.h (working copy)
@@ -222,8 +222,6 @@
void (*platform_send_init_74_clocks)(struct sdhci_host *host,
u8 power_mode);
unsigned int (*get_ro)(struct sdhci_host *host);
+ void (*shared_data_bus)(struct
sdhci_host *host,
+
int acquire);
};
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
Index: drivers/mmc/host/sdhci.c
===================================================================
--- drivers/mmc/host/sdhci.c (revision 4485)
+++ drivers/mmc/host/sdhci.c (working copy)
@@ -1124,9 +1124,6 @@
host = mmc_priv(mmc);
+ if (host->quirks & SDHCI_QUIRK_SHARE_DATA_PINS)
+ host->ops->shared_data_bus(host, 1);
+
spin_lock_irqsave(&host->lock, flags);
WARN_ON(host->mrq != NULL);
@@ -1381,9 +1378,6 @@
spin_unlock_irqrestore(&host->lock, flags);
mmc_request_done(host->mmc, mrq);
+
+ if (host->quirks & SDHCI_QUIRK_SHARE_DATA_PINS)
+ host->ops->shared_data_bus(host, 0);
}
static void sdhci_timeout_timer(unsigned long data)
My questions is
1) What’s purpose of quirks? For lots of sd/mmc host controller
different feature and IC bugs?
2) My patch has modified kernel mmc core codes to achieve my
purpose(shared 8 data pins on runtime), is it acceptable?
Any suggestion and comment will be welcome!
Best Regards,
Shi Bin
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