> At least for the sh7757 and sh7372.
Also for the sh7724 (ie, only the sh7757 can run at full bus speed by setting
CLKDIV=0xF which no other part can....yet)
But, with this new patch applied:
> if (!ret) {
> host->clk = clk_get_rate(host->hclk);
> - host->mmc->f_max = host->clk / 2;
> + host->mmc->f_max = p->sup_pclk ? host->clk : host->clk / 2;
> host->mmc->f_min = host->clk / 512;
> }
Then there's no need to check for p->sup_pclk in sh_mmcif_clock_control()
because if (clk == host->clk) then p->sup_pclk can be assumed to be set.
- if (p->sup_pclk && clk == host->clk)
+ if (clk == host->clk)
sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK);
else
sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR &
((fls(DIV_ROUND_UP(host->clk,
clk) - 1) - 1) << 16));
But, that's probably more along the lines of driver cleanup I guess.
-Chris
-----Original Message-----
From: Simon Horman [mailto:[email protected]]
Sent: Wednesday, June 20, 2012 8:48 PM
To: Brandt, Chris
Cc: Guennadi Liakhovetski; [email protected]; [email protected];
Chris Ball; Magnus Damm
Subject: Re: [PATCH] mmc: sh_mmcif: mmc->f_max heuristic
On Wed, Jun 20, 2012 at 07:56:44AM -0700, Brandt, Chris wrote:
> > I would be very happy if someone with access to
> > the documentation could shed some further light on this.
>
> According to the SH7757 manual, setting the CLKDIV[3:0] in the CE_CLK_CTRL
> register 0xF selects Pck as the bus clock frequency. So, unlike other devices
> where Pck/2 (CLKDIV[3:0]=0) is the max bus speed, the SH7757 can run at Pck
> when CLKDIV=0xF.
Thanks Chris,
please correct me if I am wrong, but that seems to indicate the heuristic
is correct. At least for the sh7757 and sh7372.
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