On Thu, Aug 23, 2012 at 12:31 PM, Jaehoon Chung <[email protected]> wrote:
> This patch is added the use_hold_reg bit in CMD register.
>
> In upper version than 2.40a, bit[29] of CMD register is used the use_hold_reg.
> Some SoC is affected by this bit.
> (This bit means whether use hold register when send data and cmd.
> And related with cclk_in_drv phase)
>
> Signed-off-by: Jaehoon Chung <[email protected]>
> Signed-off-by: Kyungmin Park <[email protected]>
> ---
> drivers/mmc/host/dw_mmc.c | 36 ++++++++++++++++++++++++++++++++++++
> drivers/mmc/host/dw_mmc.h | 1 +
> include/linux/mmc/dw_mmc.h | 3 +++
> 3 files changed, 40 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
> index feafa2d..426171f 100644
> --- a/drivers/mmc/host/dw_mmc.c
> +++ b/drivers/mmc/host/dw_mmc.c
> @@ -265,11 +265,45 @@ static u32 dw_mci_prepare_command(struct mmc_host *mmc,
> struct mmc_command *cmd)
> static void dw_mci_start_command(struct dw_mci *host,
> struct mmc_command *cmd, u32 cmd_flags)
> {
> + struct dw_mci_slot *slot = host->cur_slot;
> + struct mmc_ios *ios = &slot->mmc->ios;
> +
> host->cmd = cmd;
> dev_vdbg(&host->dev,
> "start command: ARGR=0x%08x CMDR=0x%08x\n",
> cmd->arg, cmd_flags);
>
> + if (host->quirks & DW_MCI_QUIRK_USE_CLKSEL_REG) {
> + /*
> + * If use HOLD register and SDR12/SDSR25,
> + * CMD and DATA sent to card through HOLD register by default.
> + * But if mode is SDR50/DDR50/SDR104,
> + * only use the hold register when cclk_in_drv value is upper
> than 0.
"greater" might be better than "upper" here.
> + */
> + switch (ios->timing) {
> + case MMC_TIMING_UHS_SDR50:
> + case MMC_TIMING_UHS_DDR50:
> + if (host->pdata->get_clk_drv)
> + if ((host->pdata->get_clk_drv(host) &&
> + host->use_hold_reg)) {
There's more brackets than necessary here in the second if, and the
two if conditions could probably be combined to make it neater.
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