On 08/24/2012 12:57 PM, Seungwon Jeon wrote:
> On Thursday, August 23, 2012, Jaehoon Chung <[email protected]> wrote:
>> Signed-off-by: Jaehoon Chung <[email protected]>
>> Signed-off-by: Kyungmin Park <[email protected]>
>> ---
>> include/linux/mmc/exynos-dw_mmc.h | 55
>> +++++++++++++++++++++++++++++++++++++
>> 1 files changed, 55 insertions(+), 0 deletions(-)
>> create mode 100644 include/linux/mmc/exynos-dw_mmc.h
>>
>> diff --git a/include/linux/mmc/exynos-dw_mmc.h
>> b/include/linux/mmc/exynos-dw_mmc.h
>> new file mode 100644
>> index 0000000..03444c2
>> --- /dev/null
>> +++ b/include/linux/mmc/exynos-dw_mmc.h
>> @@ -0,0 +1,55 @@
>> +/*
>> + * Synopsys DesignWare Multimedia Card Interface driver
>> + *
>> + * Copyright (c) 2012 Samsung Electronics Co., Ltd.
>> + * http://www.samsung.com
>> + *
>> + * Header file for Exynos specific register
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#ifndef _EXYNOS_DW_MMC_H
>> +#define _EXYNOS_DW_MMC_H
>> +#include <linux/mmc/dw_mmc.h>
>> +#include <linux/mmc/host.h>
>> +
>> +#define SDMMC_EXYNOS_CLKSEL 0x09C
>> +
>> +#define SDMMC_GET_CLK_DRV(x) ((x) >> 16 & 0x7)
>> +#define SDMMC_GET_CLK_SAMPLE(x) ((x) & 0x7)
>> +#define SDMMC_CLK_RESET_DRV_SAMPLE (0x00070007);
> Could you check the width of register field?
> There is some difference between ExynosX.
> It should cover all.
I checked the Exynos4 and Exynos5.
So i used the 0x7.
If i miss something, let me know.
Best Regards,
Jaehoon Chung
>
>> +
>> +#define mci_readl(dev, reg) \
>> + __raw_readl((dev)->regs + SDMMC_##reg)
>> +#define mci_writel(dev, reg, value) \
>> + __raw_writel((value), (dev)->regs + SDMMC_##reg)
>> +
>> +static inline int exynos_get_clk_drv(struct dw_mci *host)
>> +{
>> + return SDMMC_GET_CLK_DRV(mci_readl(host, EXYNOS_CLKSEL));
>> +}
>> +
>> +static inline int exynos_get_clk_sample(struct dw_mci *host)
>> +{
>> + return SDMMC_GET_CLK_DRV(mci_readl(host, EXYNOS_CLKSEL));
>> +}
>> +
>> +static inline void exynos_set_clk_drv_sample(struct dw_mci *host,
>> + struct mmc_ios *ios)
>> +{
>> + u32 regs;
>> +
>> + regs = mci_readl(host, EXYNOS_CLKSEL);
>> + regs &= ~SDMMC_CLK_RESET_DRV_SAMPLE;
>> + if (ios->timing == MMC_TIMING_UHS_DDR50)
>> + regs |= host->pdata->ddr_timing;
>> + else
>> + regs |= host->pdata->sdr_timing;
>> +
>> + mci_writel(host, EXYNOS_CLKSEL, regs);
>> +}
>> +
>> +#endif /* _EXYNOS_DW_MMC_H */
>> --
>> 1.7.4.1
>> --
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>
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