On 12/6/13 11:36 AM, Arnd Bergmann wrote: > On Friday 06 December 2013, [email protected] wrote: >> From: Dinh Nguyen <[email protected]> >> >> Hi, >> >> This patch series makes the setting of the SDMMC_CMD_USE_HOLD_REG bit generic >> for all platforms that requires it. According the Synopsys spec on the >> dw_mmc, >> setting the SDMMC_CMD_USE_HOLD_REG should be done for all speeds except for >> the >> following higher speed modes: SDR104, SDR50, DDR50. I am also include >> MMC_HS200 >> speed as not needing the SDMMC_CMD_USE_HOLD_REG bit set as well. >> >> Currently, Rockchip and SOCFPGA's variant of the dw_mmc requires that the >> SDMMC_CMD_USE_HOLD_REG be set. For SOCFPGA, the dw_mmc is operating at >> MMC_TIMING_SD_HS mode. I don't know Rockchip's variant is operating at. >> > > Very nice, thanks for implementing this! > > Acked-by: Arnd Bergmann <[email protected]> > > Obviously this needs to be tested on at least the rockchips variant, but > ideally on most others too. Thanks Arnd! But I think I will have to send out a v2 shortly. I missed a subtle line in the databook that the hold_reg should be cleared if there is no clock phase selected. I think the patch as it stands will break dw_mmc-exynos.
Dinh > > Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
