DDR mode can use with 4bit or 8bit buswidth.
Signed-off-by: Jaehoon Chung <[email protected]>
---
drivers/mmc/host/dw_mmc-exynos.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index aee39bc..0884df6 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -190,8 +190,7 @@ static void dw_mci_exynos_set_ios(struct dw_mci *host,
struct mmc_ios *ios)
if (ios->timing == MMC_TIMING_MMC_DDR52) {
mci_writel(host, CLKSEL, priv->ddr_timing);
/* Should be double rate for DDR mode */
- if (ios->bus_width == MMC_BUS_WIDTH_8)
- wanted <<= 1;
+ wanted <<= 1;
} else {
mci_writel(host, CLKSEL, priv->sdr_timing);
}
--
1.7.9.5
--
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