Hi all,
In via-rhine.c, tulip.c, rtl8139.c, eepro100.c, dgrs.c (and other net
drivers) min_pci_latency is modified to 64 or more. It triggers up the
BIOS PCI latency timer for the particular device if it's too low.
With today's motherboards, this parameter is often tuned to 32 by the
BIOS manufacturer as a default for all devices, so it's tuned up by the
driver code, each driver doing his own hack.
For example tulip.c says :
---8<---
if (pci_latency < 10) {
printk(KERN_INFO " PCI latency timer (CFLT) is "
"unreasonably low at %d. Setting to 64 clocks.\n",
pci_latency);
pcibios_write_config_byte(pci_bus, pci_device_fn,
PCI_LATENCY_TIMER, 64);
---8<---
My questions are :
Which problems arise with low latency values ? Is it just causing an
unneeded overhead somewhere ?
Does a lower pci latency improve TCP_NO_DELAY packets latency
significantly for network transfers (under MPI for example) ? In that
case does it mean I should choose a card by checking the ones that have
a lower latency hardcoded in their driver fi I want low MPI latency ?
Pierre
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