On Wed, 13 Oct 1999, Steve Shah wrote:
> On Wed, Oct 13, 1999 at 11:47:40AM -0400, Donald Becker wrote:
> > The real problem with the Hamachi is that Alcatel (which bought Packet
> > Engines for their wonderful switch design) isn't interested in the NIC
> > market and will be shutting down production on December 1.
>
> (This e-mail represents my words. Not Alteon's words. I think for myself,
> thank you.)
>
> Not that I'm biased or anything (see .sig for why) but Alteon puts out
> some nice gig nics. The driver for Linux is GPL'd and the NIC itself
> is open firmware. (You can actually write code to run on the NIC
> itself. From the top level web page, click on support, then on
> software.)
Yes, they are nice.
I think that they are a little complex:
- the downloaded firmware makes the driver very large.
- they consume more power than the Hamachi, likely due to the generality
OTOH,
- The new Cat-5 copper transceivers will dominate the power draw
(And I expected them to drop cost and power... I was so wrong.)
- Downloadable firmware means that we might get native ST, VIA or GM
implementations where the adapter interprets the packet rather than
interrupting the main processor.
> btw, the 3Com 3C985 and Netgear GA620 are the same nic. (See the the
> linux/drivers/net/acenic.c file for more details.)
Hey, wait, I didn't think that anyone admitted that!
(The GA620 has been available for under $300, far less than other GB boards.)
> With interrupt coalescence, a heavily loaded machine can have
> interrupts drop from 15,000 to less than 2,000. Fun stuff.
A number of newer chips have Rx interrupt mitigation/coalescence e.g. the
Hamachi, Starfire and 21143-TD. Presumably the new Intel chips have
something undocumented (based on nebulous marketing claims).
Most chips have static settings. Ideally the chip would do something more
clever e.g. if the last packet was large and for me (bulk traffic), wait one
IFG. If there is an immediately following packet and it's passes my Rx
filter, defer the interrupt.
On related topices, the chip should also
- measure the interrupt latency,
- report the low-water-mark for the Tx FIFO to assist tuning without
triggering underruns.
- Have variable Rx DMA thresholds, starting the Rx DMA early (predicting a
minimum-sized packet) when the Rx pipeline is empty.
Donald Becker
Scyld Computing Corporation, and
USRA-CESDIS, [EMAIL PROTECTED]
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