On Wed, Jul 11, 2018 at 1:28 PM, Vishal Verma <vishal.l.ve...@intel.com> wrote:
> The device-dax test used heuristic timeouts for distinction between
> cached and uncached accesses. The timeout was too short for emulated
> e820 on a virtual machine. Increased the cached timeout to ~30ms, which
> still keeps it significantly far from the cached time of 200ms.
> Cc: Dan Williams <dan.j.willi...@intel.com>
> Signed-off-by: Vishal Verma <vishal.l.ve...@intel.com>
> test/device-dax.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
> diff --git a/test/device-dax.c b/test/device-dax.c
> index dd92f9a..46580fc 100644
> --- a/test/device-dax.c
> +++ b/test/device-dax.c
> @@ -97,7 +97,7 @@ static void sigbus(int sig, siginfo_t *siginfo, void *d)
> * 3.00GHz where the loop, for the align == 2M case, completes in 7500us
> * when cached and 200ms when uncached.
> -#define VERIFY_TIME(x) (suseconds_t) ((ALIGN(x, SZ_2M) / SZ_4K) * 30)
> +#define VERIFY_TIME(x) (suseconds_t) ((ALIGN(x, SZ_2M) / SZ_4K) * 60)
Looks good to me, I knew it was only a matter of time before we found
an environment that violated the expectation. Any bets on if we'll
ever need to touch it again?
Reviewed-by: Dan Williams <dan.j.willi...@intel.com>
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