> >What race are you referring to? Wouldn't such a race exist >with the current code? (i.e., a shift should not cause any >further race)
Two simultaneous writes to the same register, both accessing their own halves of it. One of the writes would potentially be lost with 32 bit accesses. As far as I understand, Cortex + caches provides a mechanism for accessing device addresses in 16bit format, which prevents this kind of race condition on machine level. (Well, I must admit that my code does not really write anything to the registers so it does not cause any race condition, this is just something I did out of habit.) -Tero -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
