The test in omap2_clk_wait_ready() for DSS or CAM clocks didn't
verify that the PRCM {F,I}CLKEN1 register was in the CORE powerdomain.
Add this check in.
Signed-off-by: Paul Walmsley <[EMAIL PROTECTED]>
---
arch/arm/mach-omap2/clock.c | 10 +++++++---
1 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 59b042f..577be44 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -236,13 +236,17 @@ static void omap2_clk_wait_ready(struct clk *clk)
else
return;
- /* No check for DSS or CAM clocks on 24xx */
- /* REVISIT: This should check prcm_mod against CORE_MOD */
- if (cpu_is_omap24xx() && (reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
+ /* 24xx: DSS and CAM have no idlest bits for their target agents */
+ if (cpu_is_omap24xx() &&
+ (prcm_mod == OMAP2420_CM_REGADDR(CORE_MOD, 0) ||
+ prcm_mod == OMAP2430_CM_REGADDR(CORE_MOD, 0)) &&
+ (reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
+
if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT ||
clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT ||
clk->enable_bit == OMAP24XX_EN_CAM_SHIFT)
return;
+
}
/* REVISIT: What are the appropriate exclusions for 34XX? */
--
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