"ext Rajendra Nayak" <[EMAIL PROTECTED]> writes:
> +int set_pd_latency(struct shared_resource *resp, u32 latency)
> +{
> + u32 pd_lat_level, ind, i;
> + struct pd_latency_db *pd_lat_db;
> + struct powerdomain *pwrdm;
> +
> + pd_lat_db = resp->resource_data;
> + pwrdm = pd_lat_db->pd;
> + pd_lat_level = PD_LATENCY_OFF;
> + /* using the latency db map to the appropriate PD state */
> + for (ind = 0; ind < PD_LATENCY_MAXLEVEL; ind++)
> + if (pd_lat_db->latency[ind] < latency)
> + pd_lat_level = ind;
> +
> + resp->curr_level = pd_lat_level;
> + switch (pd_lat_level) {
> + case PWRDM_POWER_OFF:
> + case PWRDM_POWER_RET:
> + /* Errata 1.29: No transitions from INACTIVE to RET/OFF
> + * possible.
> + * Need to be taken care of here.
> + */
> + if (pwrdm_read_pwrst(pwrdm) != PWRDM_POWER_ON) {
> + /* Force the clock domains to ON */
> + for (i = 0; pwrdm->pwrdm_clkdms[i]; i++) {
> + omap2_clkdm_deny_idle(pwrdm->pwrdm_clkdms[i]);
> + omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[i]);
> + }
> + pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_ON);
> + pwrdm_set_next_pwrst(pwrdm, pd_lat_level);
> + for (i = 0; pwrdm->pwrdm_clkdms[i]; i++) {
> + omap2_clkdm_sleep(pwrdm->pwrdm_clkdms[i]);
> + omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[i]);
> + }
> + } else
> + pwrdm_set_next_pwrst(pwrdm, pd_lat_level);
You could use set_pwrdm_state from pm34xx.c here and update it if
necessary. This way your workaround for errate 1.29 would be available
for cpuidle, pm_idle, srf and suspend.
--
Jouni Högander
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