A shadow register change has no direct effect on the display
configuration until the GOLCD (DISPC_CONTROL[5]) is set.
Signed-off-by: Arun C <[EMAIL PROTECTED]>
---
drivers/video/omap/dispc.c | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c
index 82ba030..2e7af85 100644
--- a/drivers/video/omap/dispc.c
+++ b/drivers/video/omap/dispc.c
@@ -436,6 +436,11 @@ static inline int _setup_plane(int plane, int channel_out,
dispc_write_reg(ri_reg[plane], (screen_width - width) * bpp / 8 + 1);
+ /* Wait untill GOLCD bit is cleared and set it */
+ while (dispc_read_reg(DISPC_CONTROL) & (1 << 5))
+ continue;
+ MOD_REG_FLD(DISPC_CONTROL, 1 << 5, 1 << 5);
+
return height * screen_width * bpp / 8;
}
--
1.5.3.4
--
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