On Wed, Sep 10, 2008 at 05:13:03PM -0700, ext Tony Lindgren wrote:
> * Daniel Stone <[EMAIL PROTECTED]> [080827 02:47]:
> > On Wed, Aug 27, 2008 at 12:50:37AM -0600, ext Paul Walmsley wrote:
> > > Hello Daniel,
> > > 
> > > On Wed, 27 Aug 2008, Daniel Stone wrote:
> > > 
> > > > Yep, looks fine to me: just wasn't really sure what to put.  Should I
> > > > resend, or?
> > > 
> > > yes, please resend - that will make it convenient for Tony to apply the 
> > > patches.
> > 
> > Hi,
> > I'll do that.  Thanks a lot for the review.
> 
> ping, any news on the updated patch?

Sorry, my bad.  Inlined below.

Cheers,
Daniel


From d8f04561d17adc8c52f8c2d6091bc9897904feb7 Mon Sep 17 00:00:00 2001
From: Daniel Stone <[EMAIL PROTECTED]>
Date: Wed, 27 Aug 2008 04:31:59 +0300
Subject: [PATCH] ARM: OMAP2: Fix definition of SGX clock register bits

The GFX/SGX functional and interface clocks have different masks, for
some unknown reason, so split EN_SGX_SHIFT into one each for fclk and
iclk.

Correct according to the TRM and the far more important 'does this
actually work at all?' metric.

Signed-off-by: Daniel Stone <[EMAIL PROTECTED]>
---
 arch/arm/mach-omap2/clock34xx.h       |    4 ++--
 arch/arm/mach-omap2/cm-regbits-34xx.h |    8 ++++++--
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index d7d6ffd..ce96270 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -1323,7 +1323,7 @@ static struct clk sgx_fck = {
        .name           = "sgx_fck",
        .init           = &omap2_init_clksel_parent,
        .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
-       .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
+       .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
        .clksel_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
        .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
        .clksel         = sgx_clksel,
@@ -1337,7 +1337,7 @@ static struct clk sgx_ick = {
        .parent         = &l3_ick,
        .init           = &omap2_init_clk_clkdm,
        .enable_reg     = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
-       .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
+       .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
        .flags          = CLOCK_IN_OMAP3430ES2,
        .clkdm          = { .name = "sgx_clkdm" },
        .recalc         = &followparent_recalc,
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h 
b/arch/arm/mach-omap2/cm-regbits-34xx.h
index ffb695b..fe8e9ef 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -340,8 +340,12 @@
 #define OMAP3430ES1_CLKACTIVITY_GFX_MASK               (1 << 0)
 
 /* CM_FCLKEN_SGX */
-#define OMAP3430ES2_EN_SGX_SHIFT                       1
-#define OMAP3430ES2_EN_SGX_MASK                                (1 << 1)
+#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT         1
+#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK          (1 << 1)
+
+/* CM_ICLKEN_SGX */
+#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT         0
+#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK          (1 << 0)
 
 /* CM_CLKSEL_SGX */
 #define OMAP3430ES2_CLKSEL_SGX_SHIFT                   0
-- 
1.5.6.3

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