On Fri, Oct 24, 2008 at 4:19 PM, Pandita, Vikram <[EMAIL PROTECTED]> wrote:
>
> Paul
>
> I was debugging why EHCI is not coming up and getting stuck in infinite loop
> for TLL not enabling.
EHCI is still broken on the current top of tree -- same infinite loop.
Have anyone figured out what is going wrong here?
Steve
> I found that there is issue with clock framework in enabling "usbtll_fck"
> clock.
>
> On enabling tll-fck clock, the framework returns error for the node:
>
> static struct clk dpll5_ck = {
> .name = "dpll5_ck",
> .parent = &sys_ck,
> .prcm_mod = PLL_MOD,
> .dpll_data = &dpll5_dd,
> .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
> .enable = &omap3_noncore_dpll_enable,
> .disable = &omap3_noncore_dpll_disable,
> .round_rate = &omap2_dpll_round_rate,
> .set_rate = &omap3_noncore_dpll_set_rate,
> .clkdm = { .name = "dpll5_clkdm" },
> .recalc = &omap3_dpll_recalc,
> };
>
>
> If I set the FCLK for USB-TLL directly as per following patch, EHCI works
> fine.
> Please check what is wrong with the above clock node.
>
> ---
> diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c
> index 419e70a..96b9df5 100644
> --- a/drivers/usb/host/ehci-omap.c
> +++ b/drivers/usb/host/ehci-omap.c
> @@ -236,10 +236,9 @@ static int omap_start_ehc(struct platform_device *dev,
> struct usb_hcd *hcd)
> #endif
>
> /* Configure TLL for 60Mhz clk for ULPI */
> - ehci_clocks->usbtll_fck_clk = clk_get(&dev->dev, USBHOST_TLL_FCLK);
> - if (IS_ERR(ehci_clocks->usbtll_fck_clk))
> - return PTR_ERR(ehci_clocks->usbtll_fck_clk);
> - clk_enable(ehci_clocks->usbtll_fck_clk);
> +
> + /* Force enable FCLK for USB-TLL */
> + omap_writel(1<<2, 0x48004A08); /* CM_FCLKEN3_CORE */
>
> ehci_clocks->usbtll_ick_clk = clk_get(&dev->dev, USBHOST_TLL_ICKL);
> if (IS_ERR(ehci_clocks->usbtll_ick_clk))
> --
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