Enabling clock in a disabled power domain causes the power domain to be
turned on. However, the power transition is not always finished when
clk_enable() returns and this randomly crashes the kernel when an
interrupt happens right after the clk_enable, and the kernel tries to
read the irq status register for that domain.
Why the irq status register is inaccessible, I don't know. Also it
doesn't seem to be related to the module being not powered up, but to
the transition itself.
The same could perhaps happen after clk_disable also, even if I have not
witnessed that.
The problem affects at least dss, cam and sgx clocks.
This change waits for the transition to be finished before returning
from omap2_clkdm_clk_enable/disable().
Signed-off-by: Tomi Valkeinen <[EMAIL PROTECTED]>
---
arch/arm/mach-omap2/clockdomain.c | 4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/clockdomain.c
b/arch/arm/mach-omap2/clockdomain.c
index fa62f14..3ae9beb 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -567,6 +567,8 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm,
struct clk *clk)
else
omap2_clkdm_wakeup(clkdm);
+ pwrdm_wait_transition(clkdm->pwrdm.ptr);
+
return 0;
}
@@ -618,6 +620,8 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm,
struct clk *clk)
else
omap2_clkdm_sleep(clkdm);
+ pwrdm_wait_transition(clkdm->pwrdm.ptr);
+
return 0;
}
--
1.6.0.3
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