Hi Grazvydas, Steve, On Thu, 11 Dec 2008, Grazvydas Ignotas wrote:
> > Can you please post whatever patches you need to apply to make it work > > occasionally so others can also look at the issue? > > For pandora, making infinite while loops finite doesn't help much, > kernel crashes later on. Steve had this too: > http://marc.info/?l=linux-omap&m=122378604027303&w=2 > > I did bisect and found that commit > 8b1f0bd44fe490ec631230c8c040753a2bda8caa is causing the hang for me. > Reverting this makes EHCI work again on pandora. > http://marc.info/?l=linux-omap&m=122453174024860&w=2 Would one of you be willing to run with this patch and send back any debug output relating to dpll5_ck ? (Unfortunately, I don't have access to any boards with EHCI hardware, so cannot try it myself) This will help determine what fix should be applied - Paul Add debugging in omap3_noncore_dpll_enable() - for testing only. --- arch/arm/mach-omap2/clock34xx.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 2c655be..3b80667 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -275,6 +275,10 @@ static int omap3_noncore_dpll_enable(struct clk *clk) if (!dd) return -EINVAL; + pr_info("clock: %s: clk->rate = %ld, hdwr rate = %d, parent " + "rate = %ld\n", clk->name, clk->rate, + omap2_get_dpll_rate(clk), dd->bypass_clk->rate); + if (clk->rate == dd->bypass_clk->rate) r = _omap3_noncore_dpll_bypass(clk); else -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
