L3 divisor is not taken into account when trying to set DPLL3 clock.
Signed-off-by: Tero Kristo <[email protected]>
---
arch/arm/mach-omap2/clock34xx.c | 5 ++++-
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index b565ee6..8b375a9 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -959,6 +959,7 @@ static int omap3_select_table_rate(struct clk *clk,
unsigned long rate)
struct omap_opp *prcm_vdd = NULL;
unsigned long found_speed = 0, curr_mpu_speed;
int index = 0;
+ int l3_div;
if ((clk != &virt_vdd1_prcm_set) && (clk != &virt_vdd2_prcm_set))
return -EINVAL;
@@ -1000,7 +1001,9 @@ static int omap3_select_table_rate(struct clk *clk,
unsigned long rate)
curr_mpu_speed/1000, found_speed/1000);
#endif
} else {
- clk_set_rate(dpll3_clk, prcm_vdd->rate);
+ l3_div = cm_read_mod_reg(CORE_MOD, CM_CLKSEL) &
+ OMAP3430_CLKSEL_L3_MASK;
+ clk_set_rate(dpll3_clk, prcm_vdd->rate * l3_div);
curr_vdd2_prcm_set = prcm_vdd;
}
--
1.5.4.3
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