From: Hari Kanigeri <h-kanige...@ti.com>
Date: Mon, 17 Nov 2008 16:20:06 -0600
Subject: [PATCH] DSPBRIDGE: Mapping sidetone registers
New 3430 HW feature integrated into McBSP2
and McBSP3, enabling a sidetone process, for DASF.
Bridge has to handle this new configuration.
Signed-off-by: Hari Kanigeri <h-kanige...@ti.com>
---
drivers/dsp/bridge/wmd/_tiomap.h | 7 +++++++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/drivers/dsp/bridge/wmd/_tiomap.h b/drivers/dsp/bridge/wmd/_tiomap.h
index ed1bff9..5267eb2 100644
--- a/drivers/dsp/bridge/wmd/_tiomap.h
+++ b/drivers/dsp/bridge/wmd/_tiomap.h
@@ -161,6 +161,11 @@ struct MAP_L4PERIPHERAL {
#define PM_GRPSEL_BASE 0x48307000
#define DSPVA_GRPSEL_BASE 0x11821000
+#define L4_PERIPHERAL_SIDETONE_MCBSP2 0x49028000
+#define DSPVA_PERIPHERAL_SIDETONE_MCBSP2 0x11824000
+#define L4_PERIPHERAL_SIDETONE_MCBSP3 0x4902a000
+#define DSPVA_PERIPHERAL_SIDETONE_MCBSP3 0x11825000
+
/* define a static array with L4 mappings */
static const struct MAP_L4PERIPHERAL L4PeripheralTable[] = {
{L4_PERIPHERAL_MBOX, DSPVA_PERIPHERAL_MBOX},
@@ -196,6 +201,8 @@ static const struct MAP_L4PERIPHERAL L4PeripheralTable[] = {
{L4_PERIPHERAL_CM, DSPVA_PERIPHERAL_CM},
{L4_PERIPHERAL_PER, DSPVA_PERIPHERAL_PER},
{PM_GRPSEL_BASE, DSPVA_GRPSEL_BASE},
+ {L4_PERIPHERAL_SIDETONE_MCBSP2, DSPVA_PERIPHERAL_SIDETONE_MCBSP2},
+ {L4_PERIPHERAL_SIDETONE_MCBSP3, DSPVA_PERIPHERAL_SIDETONE_MCBSP3},
{L4_PERIPHERAL_NULL, DSPVA_PERIPHERAL_NULL}
};
--
1.6.0
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