>-----Original Message-----
>From: [email protected]
>[mailto:[email protected]] On Behalf Of ext Kevin Hilman
>Sent: 04.02.2009 08:10
>To: Ramesh Gupta Guntha
>Cc: [email protected]
>Subject: Re: PM branch updates: 3430sdp and omap3evm results
>
>Ramesh Gupta Guntha <[email protected]> writes:
>
>> Kevin,
>>
>>
>> On 2/4/09, Kevin Hilman <[email protected]> wrote:
>>> Ramesh Gupta Guntha <[email protected]> writes:
>>>
>>> > Hi,
>>> >
>>> >  I am able to resolve all other issues with this pm branch except
>>> > one issue,
>>> >
>>> > I am not able to enable the iva2 clock once system is
>suspended and
>>> > resumed, I am getting below messages.
>>> >>
>>> >> <3>clock: dpll2_ck failed transition to 'locked'
>>> >> clock: dpll2_ck failed transition to 'locked'
>>> >> <3>clock: dpll2_ck failed transition to 'locked'
>>> >> clock: dpll2_ck failed transition to 'locked'
>>> >
>>> > Once after booting ( without adding bridgedriver/ installing
>>> > bridgedriver)
>>> > CM_CLKEN_PLL_IVA2 value shows as 0x37 indicates IVA2 DPLL
>in locked mode.
>>> >
>>> > once after system suspend the value is not restored I am seeing
>>> > that as
>>> >  0x11 indicates IVA2 DPLL is low power stop mode.
>>> >
>>> > Can any one please provide your inputs on the above
>error? I tried
>>> > reconfiguring the CM_CLKEN_PLL_IVA2 to lock mode but still I am
>>> > seeing the same messages as above while enabling iva2 clock.
>>>
>>> Are you suspending into retention or off-mode?
>>
>> I am suspending into Off mode.
>>
>
>Do you see this problem when only going into retention?
>
>If not, sounds like we're missing some registers being
>saved/restored across off-mode.

This remids me about another issue which is with DPLL5. ROM code is not 
currently saving/restoring that. Maybe there is similar situation with DPLL2.

>
>Kevin
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