On Tue, Feb 24, 2009 at 11:50 PM, Guzman Lugo, Fernando <[email protected]> wrote:
> From 708b2a4a434408e2d5325aa360ffb2cd57bc6bd1 Mon Sep 17 00:00:00 2001
> From: Fernando Guzman Lugo <[email protected]>
> Date: Mon, 23 Feb 2009 18:12:27 -0600
> Subject: [PATCH] DSPBRIDGE: Change address resources to void __iomem *
>
> This patch changes address resources to void __iomem *
> Signed-off-by: Guzman Lugo Fernando <[email protected]>
> ---
> arch/arm/plat-omap/include/dspbridge/cfgdefs.h | 16 ++++----
> drivers/dsp/bridge/hw/hw_dspssC64P.c | 2 +-
> drivers/dsp/bridge/hw/hw_dspssC64P.h | 2 +-
> drivers/dsp/bridge/hw/hw_mbox.c | 30 +++++++------
> drivers/dsp/bridge/hw/hw_mbox.h | 18 ++++----
> drivers/dsp/bridge/hw/hw_mmu.c | 43 ++++++++++----------
> drivers/dsp/bridge/hw/hw_mmu.h | 30 +++++++-------
> drivers/dsp/bridge/hw/hw_prcm.c | 26 ++++++------
> drivers/dsp/bridge/hw/hw_prcm.h | 17 ++++----
> drivers/dsp/bridge/rmgr/drv.c | 52
> ++++++++++++------------
> drivers/dsp/bridge/rmgr/node.c | 2 +-
> drivers/dsp/bridge/wmd/_tiomap.h | 2 +-
> drivers/dsp/bridge/wmd/tiomap3430.c | 47 ++++++++++-----------
> 13 files changed, 145 insertions(+), 142 deletions(-)
>
> diff --git a/arch/arm/plat-omap/include/dspbridge/cfgdefs.h
> b/arch/arm/plat-omap/include/dspbridge/cfgdefs.h
> index ca96b3c..e7633b5
> --- a/arch/arm/plat-omap/include/dspbridge/cfgdefs.h
> +++ b/arch/arm/plat-omap/include/dspbridge/cfgdefs.h
> @@ -96,14 +96,14 @@
> u32 dwChnlOffset;
> u32 dwChnlBufSize;
> u32 dwNumChnls;
> - u32 dwPrmBase;
> - u32 dwCmBase;
> - u32 dwPerBase;
> - u32 dwWdTimerDspBase;
> - u32 dwMboxBase;
> - u32 dwDmmuBase;
> - u32 dwDipiBase;
> - u32 dwSysCtrlBase;
> + void __iomem *dwPrmBase;
> + void __iomem *dwCmBase;
> + void __iomem *dwPerBase;
> + void __iomem *dwWdTimerDspBase;
> + void __iomem *dwMboxBase;
> + void __iomem *dwDmmuBase;
> + u32 *dwDipiBase;
s/u32/void __iomem/ right?
> + void __iomem *dwSysCtrlBase;
> } ;
>
> struct CFG_DSPMEMDESC {
> diff --git a/drivers/dsp/bridge/hw/hw_dspssC64P.c
> b/drivers/dsp/bridge/hw/hw_dspssC64P.c
> index 0d0d45c..6aac57d
> --- a/drivers/dsp/bridge/hw/hw_dspssC64P.c
> +++ b/drivers/dsp/bridge/hw/hw_dspssC64P.c
> @@ -34,7 +34,7 @@
> #include <IPIAccInt.h>
>
> /* HW FUNCTIONS */
> -HW_STATUS HW_DSPSS_BootModeSet(const u32 baseAddress,
> +HW_STATUS HW_DSPSS_BootModeSet(const void __iomem *baseAddress,
> enum HW_DSPSYSC_BootMode_t bootMode,
> const u32 bootAddress)
> {
> diff --git a/drivers/dsp/bridge/hw/hw_dspssC64P.h
> b/drivers/dsp/bridge/hw/hw_dspssC64P.h
> index 493effd..50f9af4
> --- a/drivers/dsp/bridge/hw/hw_dspssC64P.h
> +++ b/drivers/dsp/bridge/hw/hw_dspssC64P.h
> @@ -41,7 +41,7 @@
>
> #define HW_DSP_IDLEBOOT_ADDR 0x007E0000
>
> - extern HW_STATUS HW_DSPSS_BootModeSet(const u32 baseAddress,
> + extern HW_STATUS HW_DSPSS_BootModeSet(const void __iomem *baseAddress,
> enum HW_DSPSYSC_BootMode_t bootMode,
> const u32 bootAddress);
>
> diff --git a/drivers/dsp/bridge/hw/hw_mbox.c b/drivers/dsp/bridge/hw/hw_mbox.c
> index bc61d64..93fa51e
> --- a/drivers/dsp/bridge/hw/hw_mbox.c
> +++ b/drivers/dsp/bridge/hw/hw_mbox.c
> @@ -26,6 +26,7 @@
> */
>
> #include <GlobalTypes.h>
> +#include <linux/io.h>
> #include "MLBRegAcM.h"
> #include <hw_defs.h>
> #include <hw_mbox.h>
> @@ -36,7 +37,7 @@
> struct MAILBOX_CONTEXT mboxsetting = {0x4, 0x1, 0x1};
>
> /* Saves the mailbox context */
> -HW_STATUS HW_MBOX_saveSettings(u32 baseAddress)
> +HW_STATUS HW_MBOX_saveSettings(void __iomem *baseAddress)
> {
> HW_STATUS status = RET_OK;
>
> @@ -50,7 +51,7 @@ HW_STATUS HW_MBOX_saveSettings(u32 baseAddress)
> }
>
> /* Restores the mailbox context */
> -HW_STATUS HW_MBOX_restoreSettings(u32 baseAddress)
> +HW_STATUS HW_MBOX_restoreSettings(void __iomem *baseAddress)
> {
> HW_STATUS status = RET_OK;
> /* Restor IRQ enable status */
> @@ -65,8 +66,8 @@ HW_STATUS HW_MBOX_restoreSettings(u32 baseAddress)
>
> /* Reads a u32 from the sub module message box Specified. if there are no
> * messages in the mailbox then and error is returned. */
> -HW_STATUS HW_MBOX_MsgRead(const u32 baseAddress, const HW_MBOX_Id_t
> mailBoxId,
> - u32 *const pReadValue)
> +HW_STATUS HW_MBOX_MsgRead(const void __iomem *baseAddress,
> + const HW_MBOX_Id_t mailBoxId, u32 *const pReadValue)
> {
> HW_STATUS status = RET_OK;
>
> @@ -86,8 +87,8 @@ HW_STATUS HW_MBOX_MsgRead(const u32 baseAddress, const
> HW_MBOX_Id_t mailBoxId,
> }
>
> /* Writes a u32 from the sub module message box Specified. */
> -HW_STATUS HW_MBOX_MsgWrite(const u32 baseAddress, const HW_MBOX_Id_t
> mailBoxId,
> - const u32 writeValue)
> +HW_STATUS HW_MBOX_MsgWrite(const void __iomem *baseAddress,
> + const HW_MBOX_Id_t mailBoxId, const u32 writeValue)
> {
> HW_STATUS status = RET_OK;
>
> @@ -105,8 +106,8 @@ HW_STATUS HW_MBOX_MsgWrite(const u32 baseAddress, const
> HW_MBOX_Id_t mailBoxId,
> }
>
> /* Reads the full status register for mailbox. */
> -HW_STATUS HW_MBOX_IsFull(const u32 baseAddress, const HW_MBOX_Id_t mailBoxId,
> - u32 *const pIsFull)
> +HW_STATUS HW_MBOX_IsFull(const void __iomem *baseAddress,
> + const HW_MBOX_Id_t mailBoxId, u32 *const pIsFull)
> {
> HW_STATUS status = RET_OK;
> u32 fullStatus;
> @@ -130,8 +131,8 @@ HW_STATUS HW_MBOX_IsFull(const u32 baseAddress, const
> HW_MBOX_Id_t mailBoxId,
> }
>
> /* Gets number of messages in a specified mailbox. */
> -HW_STATUS HW_MBOX_NumMsgGet(const u32 baseAddress, const HW_MBOX_Id_t
> mailBoxId,
> - u32 *const pNumMsg)
> +HW_STATUS HW_MBOX_NumMsgGet(const void __iomem *baseAddress,
> + const HW_MBOX_Id_t mailBoxId, u32 *const pNumMsg)
> {
> HW_STATUS status = RET_OK;
>
> @@ -152,7 +153,7 @@ HW_STATUS HW_MBOX_NumMsgGet(const u32 baseAddress, const
> HW_MBOX_Id_t mailBoxId,
> }
>
> /* Enables the specified IRQ. */
> -HW_STATUS HW_MBOX_EventEnable(const u32 baseAddress,
> +HW_STATUS HW_MBOX_EventEnable(const void __iomem *baseAddress,
> const HW_MBOX_Id_t mailBoxId,
> const HW_MBOX_UserId_t userId,
> const u32 events)
> @@ -192,7 +193,7 @@ HW_STATUS HW_MBOX_EventEnable(const u32 baseAddress,
> }
>
> /* Disables the specified IRQ. */
> -HW_STATUS HW_MBOX_EventDisable(const u32 baseAddress,
> +HW_STATUS HW_MBOX_EventDisable(const void __iomem *baseAddress,
> const HW_MBOX_Id_t mailBoxId,
> const HW_MBOX_UserId_t userId,
> const u32 events)
> @@ -226,8 +227,9 @@ HW_STATUS HW_MBOX_EventDisable(const u32 baseAddress,
> }
>
> /* Sets the status of the specified IRQ. */
> -HW_STATUS HW_MBOX_EventAck(const u32 baseAddress, const HW_MBOX_Id_t
> mailBoxId,
> - const HW_MBOX_UserId_t userId, const u32 event)
> +HW_STATUS HW_MBOX_EventAck(const void __iomem *baseAddress,
> + const HW_MBOX_Id_t mailBoxId, const HW_MBOX_UserId_t userId,
> + const u32 event)
> {
> HW_STATUS status = RET_OK;
> u32 irqStatusReg;
> diff --git a/drivers/dsp/bridge/hw/hw_mbox.h b/drivers/dsp/bridge/hw/hw_mbox.h
> index 225fb40..5d3d18f
> --- a/drivers/dsp/bridge/hw/hw_mbox.h
> +++ b/drivers/dsp/bridge/hw/hw_mbox.h
> @@ -92,7 +92,7 @@ struct MAILBOX_CONTEXT {
> * box Specified. if there are no messages in the mailbox
> * then and error is returned.
> */
> -extern HW_STATUS HW_MBOX_MsgRead(const u32 baseAddress,
> +extern HW_STATUS HW_MBOX_MsgRead(const void __iomem *baseAddress,
> const HW_MBOX_Id_t mailBoxId,
> u32 *const pReadValue);
>
> @@ -124,7 +124,7 @@ extern HW_STATUS HW_MBOX_MsgRead(const u32 baseAddress,
> * box Specified.
> */
> extern HW_STATUS HW_MBOX_MsgWrite(
> - const u32 baseAddress,
> + const void __iomem *baseAddress,
> const HW_MBOX_Id_t mailBoxId,
> const u32 writeValue
> );
> @@ -159,7 +159,7 @@ extern HW_STATUS HW_MBOX_MsgWrite(
> * PURPOSE: : this function reads the full status register for mailbox.
> */
> extern HW_STATUS HW_MBOX_IsFull(
> - const u32 baseAddress,
> + const void __iomem *baseAddress,
> const HW_MBOX_Id_t mailBoxId,
> u32 *const pIsFull
> );
> @@ -193,7 +193,7 @@ extern HW_STATUS HW_MBOX_IsFull(
> * PURPOSE: : this function gets number of messages in a specified
> mailbox.
> */
> extern HW_STATUS HW_MBOX_NumMsgGet(
> - const u32 baseAddress,
> + const void __iomem *baseAddress,
> const HW_MBOX_Id_t mailBoxId,
> u32 *const pNumMsg
> );
> @@ -229,7 +229,7 @@ extern HW_STATUS HW_MBOX_NumMsgGet(
> * PURPOSE: : this function enables the specified IRQ.
> */
> extern HW_STATUS HW_MBOX_EventEnable(
> - const u32 baseAddress,
> + const void __iomem *baseAddress,
> const HW_MBOX_Id_t mailBoxId,
> const HW_MBOX_UserId_t userId,
> const u32 events
> @@ -266,7 +266,7 @@ extern HW_STATUS HW_MBOX_EventEnable(
> * PURPOSE: : this function disables the specified IRQ.
> */
> extern HW_STATUS HW_MBOX_EventDisable(
> - const u32 baseAddress,
> + const void __iomem *baseAddress,
> const HW_MBOX_Id_t mailBoxId,
> const HW_MBOX_UserId_t userId,
> const u32 events
> @@ -305,7 +305,7 @@ extern HW_STATUS HW_MBOX_EventDisable(
> * PURPOSE: : this function sets the status of the specified IRQ.
> */
> extern HW_STATUS HW_MBOX_EventAck(
> - const u32 baseAddress,
> + const void __iomem *baseAddress,
> const HW_MBOX_Id_t mailBoxId,
> const HW_MBOX_UserId_t userId,
> const u32 event
> @@ -331,7 +331,7 @@ extern HW_STATUS HW_MBOX_EventAck(
> *
> * PURPOSE: : this function saves the context of mailbox
> */
> -extern HW_STATUS HW_MBOX_saveSettings(u32 baseAddres);
> +extern HW_STATUS HW_MBOX_saveSettings(void __iomem *baseAddres);
>
> /*
> * FUNCTION : HW_MBOX_restoreSettings
> @@ -353,6 +353,6 @@ extern HW_STATUS HW_MBOX_saveSettings(u32 baseAddres);
> *
> * PURPOSE: : this function restores the context of mailbox
> */
> -extern HW_STATUS HW_MBOX_restoreSettings(u32 baseAddres);
> +extern HW_STATUS HW_MBOX_restoreSettings(void __iomem *baseAddres);
>
> #endif /* __MBOX_H */
> diff --git a/drivers/dsp/bridge/hw/hw_mmu.c b/drivers/dsp/bridge/hw/hw_mmu.c
> index da7e092..3f2b75c
> --- a/drivers/dsp/bridge/hw/hw_mmu.c
> +++ b/drivers/dsp/bridge/hw/hw_mmu.c
> @@ -30,6 +30,7 @@
> */
>
> #include <GlobalTypes.h>
> +#include <linux/io.h>
> #include "MMURegAcM.h"
> #include <hw_defs.h>
> #include <hw_mmu.h>
> @@ -79,7 +80,7 @@ enum HW_MMUPageSize_t {
> * METHOD: : Check the Input parameter and Flush a
> * single entry in the TLB.
> */
> -static HW_STATUS MMU_FlushEntry(const u32 baseAddress);
> +static HW_STATUS MMU_FlushEntry(const void __iomem *baseAddress);
>
> /*
> * FUNCTION : MMU_SetCAMEntry
> @@ -121,7 +122,7 @@ static HW_STATUS MMU_FlushEntry(const u32 baseAddress);
> *
> * METHOD: : Check the Input parameters and set the CAM entry.
> */
> -static HW_STATUS MMU_SetCAMEntry(const u32 baseAddress,
> +static HW_STATUS MMU_SetCAMEntry(const void __iomem *baseAddress,
> const u32 pageSize,
> const u32 preservedBit,
> const u32 validBit,
> @@ -166,7 +167,7 @@ static HW_STATUS MMU_SetCAMEntry(const u32 baseAddress,
> *
> * METHOD: : Check the Input parameters and set the RAM entry.
> */
> -static HW_STATUS MMU_SetRAMEntry(const u32 baseAddress,
> +static HW_STATUS MMU_SetRAMEntry(const void __iomem *baseAddress,
> const u32 physicalAddr,
> enum HW_Endianism_t endianism,
> enum HW_ElementSize_t elementSize,
> @@ -174,7 +175,7 @@ static HW_STATUS MMU_SetRAMEntry(const u32 baseAddress,
>
> /* HW FUNCTIONS */
>
> -HW_STATUS HW_MMU_Enable(const u32 baseAddress)
> +HW_STATUS HW_MMU_Enable(const void __iomem *baseAddress)
> {
> HW_STATUS status = RET_OK;
>
> @@ -183,7 +184,7 @@ HW_STATUS HW_MMU_Enable(const u32 baseAddress)
> return status;
> }
>
> -HW_STATUS HW_MMU_Disable(const u32 baseAddress)
> +HW_STATUS HW_MMU_Disable(const void __iomem *baseAddress)
> {
> HW_STATUS status = RET_OK;
>
> @@ -192,7 +193,7 @@ HW_STATUS HW_MMU_Disable(const u32 baseAddress)
> return status;
> }
>
> -HW_STATUS HW_MMU_NumLockedSet(const u32 baseAddress,
> +HW_STATUS HW_MMU_NumLockedSet(const void __iomem *baseAddress,
> u32 numLockedEntries)
> {
> HW_STATUS status = RET_OK;
> @@ -202,7 +203,7 @@ HW_STATUS HW_MMU_NumLockedSet(const u32 baseAddress,
> return status;
> }
>
> -HW_STATUS HW_MMU_VictimNumSet(const u32 baseAddress,
> +HW_STATUS HW_MMU_VictimNumSet(const void __iomem *baseAddress,
> u32 victimEntryNum)
> {
> HW_STATUS status = RET_OK;
> @@ -212,7 +213,7 @@ HW_STATUS HW_MMU_VictimNumSet(const u32 baseAddress,
> return status;
> }
>
> -HW_STATUS HW_MMU_TLBFlushAll(const u32 baseAddress)
> +HW_STATUS HW_MMU_TLBFlushAll(const void __iomem *baseAddress)
> {
> HW_STATUS status = RET_OK;
>
> @@ -221,7 +222,7 @@ HW_STATUS HW_MMU_TLBFlushAll(const u32 baseAddress)
> return status;
> }
>
> -HW_STATUS HW_MMU_EventAck(const u32 baseAddress, u32 irqMask)
> +HW_STATUS HW_MMU_EventAck(const void __iomem *baseAddress, u32 irqMask)
> {
> HW_STATUS status = RET_OK;
>
> @@ -230,7 +231,7 @@ HW_STATUS HW_MMU_EventAck(const u32 baseAddress, u32
> irqMask)
> return status;
> }
>
> -HW_STATUS HW_MMU_EventDisable(const u32 baseAddress,
> +HW_STATUS HW_MMU_EventDisable(const void __iomem *baseAddress,
> u32 irqMask)
> {
> HW_STATUS status = RET_OK;
> @@ -243,7 +244,7 @@ HW_STATUS HW_MMU_EventDisable(const u32 baseAddress,
> return status;
> }
>
> -HW_STATUS HW_MMU_EventEnable(const u32 baseAddress, u32 irqMask)
> +HW_STATUS HW_MMU_EventEnable(const void __iomem *baseAddress, u32 irqMask)
> {
> HW_STATUS status = RET_OK;
> u32 irqReg;
> @@ -256,7 +257,7 @@ HW_STATUS HW_MMU_EventEnable(const u32 baseAddress, u32
> irqMask)
> }
>
>
> -HW_STATUS HW_MMU_EventStatus(const u32 baseAddress, u32 *irqMask)
> +HW_STATUS HW_MMU_EventStatus(const void __iomem *baseAddress, u32 *irqMask)
> {
> HW_STATUS status = RET_OK;
>
> @@ -266,7 +267,7 @@ HW_STATUS HW_MMU_EventStatus(const u32 baseAddress, u32
> *irqMask)
> }
>
>
> -HW_STATUS HW_MMU_FaultAddrRead(const u32 baseAddress, u32 *addr)
> +HW_STATUS HW_MMU_FaultAddrRead(const void __iomem *baseAddress, u32 *addr)
> {
> HW_STATUS status = RET_OK;
>
> @@ -280,7 +281,7 @@ HW_STATUS HW_MMU_FaultAddrRead(const u32 baseAddress, u32
> *addr)
> return status;
> }
>
> -HW_STATUS HW_MMU_TTBSet(const u32 baseAddress, u32 TTBPhysAddr)
> +HW_STATUS HW_MMU_TTBSet(const void __iomem *baseAddress, u32 TTBPhysAddr)
> {
> HW_STATUS status = RET_OK;
> u32 loadTTB;
> @@ -296,7 +297,7 @@ HW_STATUS HW_MMU_TTBSet(const u32 baseAddress, u32
> TTBPhysAddr)
> return status;
> }
>
> -HW_STATUS HW_MMU_TWLEnable(const u32 baseAddress)
> +HW_STATUS HW_MMU_TWLEnable(const void __iomem *baseAddress)
> {
> HW_STATUS status = RET_OK;
>
> @@ -305,7 +306,7 @@ HW_STATUS HW_MMU_TWLEnable(const u32 baseAddress)
> return status;
> }
>
> -HW_STATUS HW_MMU_TWLDisable(const u32 baseAddress)
> +HW_STATUS HW_MMU_TWLDisable(const void __iomem *baseAddress)
> {
> HW_STATUS status = RET_OK;
>
> @@ -314,7 +315,7 @@ HW_STATUS HW_MMU_TWLDisable(const u32 baseAddress)
> return status;
> }
>
> -HW_STATUS HW_MMU_TLBFlush(const u32 baseAddress, u32 virtualAddr,
> +HW_STATUS HW_MMU_TLBFlush(const void __iomem *baseAddress, u32 virtualAddr,
> u32 pageSize)
> {
> HW_STATUS status = RET_OK;
> @@ -352,7 +353,7 @@ HW_STATUS HW_MMU_TLBFlush(const u32 baseAddress, u32
> virtualAddr,
> return status;
> }
>
> -HW_STATUS HW_MMU_TLBAdd(const u32 baseAddress,
> +HW_STATUS HW_MMU_TLBAdd(const void __iomem *baseAddress,
> u32 physicalAddr,
> u32 virtualAddr,
> u32 pageSize,
> @@ -538,7 +539,7 @@ HW_STATUS HW_MMU_PteClear(const u32 pgTblVa,
> }
>
> /* MMU_FlushEntry */
> -static HW_STATUS MMU_FlushEntry(const u32 baseAddress)
> +static HW_STATUS MMU_FlushEntry(const void __iomem *baseAddress)
> {
> HW_STATUS status = RET_OK;
> u32 flushEntryData = 0x1;
> @@ -554,7 +555,7 @@ static HW_STATUS MMU_FlushEntry(const u32 baseAddress)
> }
>
> /* MMU_SetCAMEntry */
> -static HW_STATUS MMU_SetCAMEntry(const u32 baseAddress,
> +static HW_STATUS MMU_SetCAMEntry(const void __iomem *baseAddress,
> const u32 pageSize,
> const u32 preservedBit,
> const u32 validBit,
> @@ -578,7 +579,7 @@ static HW_STATUS MMU_SetCAMEntry(const u32 baseAddress,
> }
>
> /* MMU_SetRAMEntry */
> -static HW_STATUS MMU_SetRAMEntry(const u32 baseAddress,
> +static HW_STATUS MMU_SetRAMEntry(const void __iomem *baseAddress,
> const u32 physicalAddr,
> enum HW_Endianism_t endianism,
> enum HW_ElementSize_t elementSize,
> diff --git a/drivers/dsp/bridge/hw/hw_mmu.h b/drivers/dsp/bridge/hw/hw_mmu.h
> index 924f32b..dc1aec1
> --- a/drivers/dsp/bridge/hw/hw_mmu.h
> +++ b/drivers/dsp/bridge/hw/hw_mmu.h
> @@ -53,47 +53,47 @@ struct HW_MMUMapAttrs_t {
> enum HW_MMUMixedSize_t mixedSize;
> } ;
>
> -extern HW_STATUS HW_MMU_Enable(const u32 baseAddress);
> +extern HW_STATUS HW_MMU_Enable(const void __iomem *baseAddress);
>
> -extern HW_STATUS HW_MMU_Disable(const u32 baseAddress);
> +extern HW_STATUS HW_MMU_Disable(const void __iomem *baseAddress);
>
> -extern HW_STATUS HW_MMU_NumLockedSet(const u32 baseAddress,
> +extern HW_STATUS HW_MMU_NumLockedSet(const void __iomem *baseAddress,
> u32 numLockedEntries);
>
> -extern HW_STATUS HW_MMU_VictimNumSet(const u32 baseAddress,
> +extern HW_STATUS HW_MMU_VictimNumSet(const void __iomem *baseAddress,
> u32 victimEntryNum);
>
> /* For MMU faults */
> -extern HW_STATUS HW_MMU_EventAck(const u32 baseAddress,
> +extern HW_STATUS HW_MMU_EventAck(const void __iomem *baseAddress,
> u32 irqMask);
>
> -extern HW_STATUS HW_MMU_EventDisable(const u32 baseAddress,
> +extern HW_STATUS HW_MMU_EventDisable(const void __iomem *baseAddress,
> u32 irqMask);
>
> -extern HW_STATUS HW_MMU_EventEnable(const u32 baseAddress,
> +extern HW_STATUS HW_MMU_EventEnable(const void __iomem *baseAddress,
> u32 irqMask);
>
> -extern HW_STATUS HW_MMU_EventStatus(const u32 baseAddress,
> +extern HW_STATUS HW_MMU_EventStatus(const void __iomem *baseAddress,
> u32 *irqMask);
>
> -extern HW_STATUS HW_MMU_FaultAddrRead(const u32 baseAddress,
> +extern HW_STATUS HW_MMU_FaultAddrRead(const void __iomem *baseAddress,
> u32 *addr);
>
> /* Set the TT base address */
> -extern HW_STATUS HW_MMU_TTBSet(const u32 baseAddress,
> +extern HW_STATUS HW_MMU_TTBSet(const void __iomem *baseAddress,
> u32 TTBPhysAddr);
>
> -extern HW_STATUS HW_MMU_TWLEnable(const u32 baseAddress);
> +extern HW_STATUS HW_MMU_TWLEnable(const void __iomem *baseAddress);
>
> -extern HW_STATUS HW_MMU_TWLDisable(const u32 baseAddress);
> +extern HW_STATUS HW_MMU_TWLDisable(const void __iomem *baseAddress);
>
> -extern HW_STATUS HW_MMU_TLBFlush(const u32 baseAddress,
> +extern HW_STATUS HW_MMU_TLBFlush(const void __iomem *baseAddress,
> u32 virtualAddr,
> u32 pageSize);
>
> -extern HW_STATUS HW_MMU_TLBFlushAll(const u32 baseAddress);
> +extern HW_STATUS HW_MMU_TLBFlushAll(const void __iomem *baseAddress);
>
> -extern HW_STATUS HW_MMU_TLBAdd(const u32 baseAddress,
> +extern HW_STATUS HW_MMU_TLBAdd(const void __iomem *baseAddress,
> u32 physicalAddr,
> u32 virtualAddr,
> u32 pageSize,
> diff --git a/drivers/dsp/bridge/hw/hw_prcm.c b/drivers/dsp/bridge/hw/hw_prcm.c
> index 61ff08f..8f04a70
> --- a/drivers/dsp/bridge/hw/hw_prcm.c
> +++ b/drivers/dsp/bridge/hw/hw_prcm.c
> @@ -29,21 +29,21 @@
> #include <hw_defs.h>
> #include <hw_prcm.h>
>
> -static HW_STATUS HW_RST_WriteVal(const u32 baseAddress,
> +static HW_STATUS HW_RST_WriteVal(const void __iomem *baseAddress,
> enum HW_RstModule_t r,
> enum HW_SetClear_t val);
>
> -HW_STATUS HW_RST_Reset(const u32 baseAddress, enum HW_RstModule_t r)
> +HW_STATUS HW_RST_Reset(const void __iomem *baseAddress, enum HW_RstModule_t
> r)
> {
> return HW_RST_WriteVal(baseAddress, r, HW_SET);
> }
>
> -HW_STATUS HW_RST_UnReset(const u32 baseAddress, enum HW_RstModule_t r)
> +HW_STATUS HW_RST_UnReset(const void __iomem *baseAddress, enum
> HW_RstModule_t r)
> {
> return HW_RST_WriteVal(baseAddress, r, HW_CLEAR);
> }
>
> -static HW_STATUS HW_RST_WriteVal(const u32 baseAddress,
> +static HW_STATUS HW_RST_WriteVal(const void __iomem *baseAddress,
> enum HW_RstModule_t r,
> enum HW_SetClear_t val)
> {
> @@ -66,8 +66,8 @@ static HW_STATUS HW_RST_WriteVal(const u32 baseAddress,
> return status;
> }
>
> -HW_STATUS HW_PWR_IVA2StateGet(const u32 baseAddress, enum HW_PwrModule_t p,
> - enum HW_PwrState_t *value)
> +HW_STATUS HW_PWR_IVA2StateGet(const void __iomem *baseAddress,
> + enum HW_PwrModule_t p, enum HW_PwrState_t *value)
> {
> HW_STATUS status = RET_OK;
> u32 temp;
> @@ -93,7 +93,7 @@ HW_STATUS HW_PWR_IVA2StateGet(const u32 baseAddress, enum
> HW_PwrModule_t p,
> return status;
> }
>
> -HW_STATUS HW_PWRST_IVA2RegGet(const u32 baseAddress, u32 *value)
> +HW_STATUS HW_PWRST_IVA2RegGet(const void __iomem *baseAddress, u32 *value)
> {
> HW_STATUS status = RET_OK;
>
> @@ -103,7 +103,7 @@ HW_STATUS HW_PWRST_IVA2RegGet(const u32 baseAddress, u32
> *value)
> }
>
>
> -HW_STATUS HW_PWR_IVA2PowerStateSet(const u32 baseAddress,
> +HW_STATUS HW_PWR_IVA2PowerStateSet(const void __iomem *baseAddress,
> enum HW_PwrModule_t p,
> enum HW_PwrState_t value)
> {
> @@ -135,7 +135,7 @@ HW_STATUS HW_PWR_IVA2PowerStateSet(const u32 baseAddress,
> return status;
> }
>
> -HW_STATUS HW_PWR_CLKCTRL_IVA2RegSet(const u32 baseAddress,
> +HW_STATUS HW_PWR_CLKCTRL_IVA2RegSet(const void __iomem *baseAddress,
> enum HW_TransitionState_t val)
> {
> HW_STATUS status = RET_OK;
> @@ -146,8 +146,8 @@ HW_STATUS HW_PWR_CLKCTRL_IVA2RegSet(const u32 baseAddress,
>
> }
>
> -HW_STATUS HW_RSTST_RegGet(const u32 baseAddress, enum HW_RstModule_t m,
> - u32 *value)
> +HW_STATUS HW_RSTST_RegGet(const void __iomem *baseAddress,
> + enum HW_RstModule_t m, u32 *value)
> {
> HW_STATUS status = RET_OK;
>
> @@ -156,8 +156,8 @@ HW_STATUS HW_RSTST_RegGet(const u32 baseAddress, enum
> HW_RstModule_t m,
> return status;
> }
>
> -HW_STATUS HW_RSTCTRL_RegGet(const u32 baseAddress, enum HW_RstModule_t m,
> - u32 *value)
> +HW_STATUS HW_RSTCTRL_RegGet(const void __iomem *baseAddress,
> + enum HW_RstModule_t m, u32 *value)
> {
> HW_STATUS status = RET_OK;
>
> diff --git a/drivers/dsp/bridge/hw/hw_prcm.h b/drivers/dsp/bridge/hw/hw_prcm.h
> index 928486c..65c8bd1
> --- a/drivers/dsp/bridge/hw/hw_prcm.h
> +++ b/drivers/dsp/bridge/hw/hw_prcm.h
> @@ -132,16 +132,16 @@ enum HW_TransitionState_t {
> } ;
>
>
> -extern HW_STATUS HW_RST_Reset(const u32 baseAddress,
> +extern HW_STATUS HW_RST_Reset(const void __iomem *baseAddress,
> enum HW_RstModule_t r);
>
> -extern HW_STATUS HW_RST_UnReset(const u32 baseAddress,
> +extern HW_STATUS HW_RST_UnReset(const void __iomem *baseAddress,
> enum HW_RstModule_t r);
>
> -extern HW_STATUS HW_RSTCTRL_RegGet(const u32 baseAddress,
> +extern HW_STATUS HW_RSTCTRL_RegGet(const void __iomem *baseAddress,
> enum HW_RstModule_t p,
> u32 *value);
> -extern HW_STATUS HW_RSTST_RegGet(const u32 baseAddress,
> +extern HW_STATUS HW_RSTST_RegGet(const void __iomem *baseAddress,
> enum HW_RstModule_t p, u32 *value);
>
> extern HW_STATUS HW_PWR_PowerStateSet(const u32 baseAddress,
> @@ -152,17 +152,18 @@ extern HW_STATUS HW_CLK_SetInputClock(const u32
> baseAddress,
> enum HW_GPtimer_t gpt,
> enum HW_Clocktype_t c);
>
> -extern HW_STATUS HW_PWR_IVA2StateGet(const u32 baseAddress,
> +extern HW_STATUS HW_PWR_IVA2StateGet(const void __iomem *baseAddress,
> enum HW_PwrModule_t p,
> enum HW_PwrState_t *value);
>
> -extern HW_STATUS HW_PWRST_IVA2RegGet(const u32 baseAddress, u32 *value);
> +extern HW_STATUS HW_PWRST_IVA2RegGet(const void __iomem *baseAddress,
> + u32 *value);
>
> -extern HW_STATUS HW_PWR_IVA2PowerStateSet(const u32 baseAddress,
> +extern HW_STATUS HW_PWR_IVA2PowerStateSet(const void __iomem *baseAddress,
> enum HW_PwrModule_t p,
> enum HW_PwrState_t value);
>
> -extern HW_STATUS HW_PWR_CLKCTRL_IVA2RegSet(const u32 baseAddress,
> +extern HW_STATUS HW_PWR_CLKCTRL_IVA2RegSet(const void __iomem *baseAddress,
> enum HW_TransitionState_t val);
>
> #endif /* __HW_PRCM_H */
> diff --git a/drivers/dsp/bridge/rmgr/drv.c b/drivers/dsp/bridge/rmgr/drv.c
> index 22faf49..07fde81
> --- a/drivers/dsp/bridge/rmgr/drv.c
> +++ b/drivers/dsp/bridge/rmgr/drv.c
> @@ -1649,15 +1649,15 @@ static DSP_STATUS RequestBridgeResources(u32
> dwContext, s32 bRequest)
> "%x. Not calling MEM_FreePhysMem\n",
> status);
> }
> - pResources->dwMemBase[1] = 0;
> - pResources->dwMemPhys[1] = 0;
> + pResources->dwMemBase[1] = (u32)NULL;
> + pResources->dwMemPhys[1] = (u32)NULL;
Why wasn't dwMemBase updated too?
<snip/>
A step in the right direction. Thanks.
--
Felipe Contreras
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