On 02/17/2014 01:27 PM, Florian Vaussard wrote:
Add the gpmc_fck clock, derived from l3_ick, and reference it from
the GPMC node to get it correctly working.

Signed-off-by: Florian Vaussard <[email protected]>
---
  arch/arm/boot/dts/omap4.dtsi           | 2 ++
  arch/arm/boot/dts/omap44xx-clocks.dtsi | 6 ++++++
  2 files changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index d3f8a6e..8a0cc71 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -275,6 +275,8 @@
                        gpmc,num-waitpins = <4>;
                        ti,hwmods = "gpmc";
                        ti,no-idle-on-init;
+                       clocks = <&gpmc_fck>;
+                       clock-names = "fck";
                };

                uart1: serial@4806a000 {
diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi 
b/arch/arm/boot/dts/omap44xx-clocks.dtsi
index c821ff5..ae2c441 100644
--- a/arch/arm/boot/dts/omap44xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
@@ -1036,6 +1036,12 @@
                ti,index-power-of-two;
        };

+       gpmc_fck: gpmc_fck {
+               #clock-cells = <0>;
+               compatible = "ti,clkdm-gate-clock";
+               clocks = <&l3_div_ck>;
+       };
+

Why not implement a proper gate clock for CM_L3_2_GPMC_CLKCTRL? The approach you have taken looks good to me otherwise.

-Tero

        gpio2_dbclk: gpio2_dbclk {
                #clock-cells = <0>;
                compatible = "ti,gate-clock";


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