On Thursday 08 May 2014 18:05:11 Jingoo Han wrote: > On Tuesday, May 06, 2014 10:59 PM, Arnd Bergmann wrote: > > On Tuesday 06 May 2014 19:03:52 Kishon Vijay Abraham I wrote: > > > In DRA7, the cpu sees 32bit address, but the pcie controller can see only > > > 28bit > > > address. So whenever the cpu issues a read/write request, the 4 most > > > significant bits are used by L3 to determine the target controller. > > > For example, the cpu reserves 0x2000_0000 - 0x2FFF_FFFF for PCIe > > > controller but > > > the PCIe controller will see only (0x000_0000 - 0xFFF_FFF). So for > > > programming > > > the outbound translation window the *base* should be programmed as > > > 0x000_0000. > > > Whenever we try to write to say 0x2000_0000, it will be translated to > > > whatever > > > we have programmed in the translation window with base as 0x000_0000. > > > > > > Cc: Bjorn Helgaas <[email protected]> > > > Cc: Marek Vasut <[email protected]> > > > Signed-off-by: Kishon Vijay Abraham I <[email protected]> > > > Acked-by: Jingoo Han <[email protected]> > > > Acked-by: Mohit Kumar <[email protected]> > > > > Sorry, but NAK. > > > > We have a standard 'dma-ranges' property to handle this, so use it. > > > > See the x-gene PCIe driver patches for an example. Please also talk > > to Santosh about it, as he is implementing generic support for > > parsing dma-ranges in platform devices at the moment. > > Hi Arnd, > > Do you mean the following patch? > http://www.spinics.net/lists/kernel/msg1737725.html >
That is the patch Santosh did for platform devices, which is related but not what I meant here. For the PCI inbound window setup, please have a look at https://lkml.org/lkml/2014/3/19/607 Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
