On 05/29/2014 09:38 AM, Kishon Vijay Abraham I wrote:
Added missing 32khz clock used by PCIe PHY. The documention for this node can be found @ ../bindings/clock/ti/gate.txt.
You can drop the node documentation ref, and rather add a TRM reference about hardware details. Other than that, looks good to me.
-Tero
Cc: Tony Lindgren <[email protected]> Cc: Rajendra Nayak <[email protected]> Cc: Tero Kristo <[email protected]> Cc: Paul Walmsley <[email protected]> Cc: Tony Lindgren <[email protected]> Cc: Rob Herring <[email protected]> Cc: Pawel Moll <[email protected]> Cc: Mark Rutland <[email protected]> Cc: Kumar Gala <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]> --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 44993ec..e1bd052 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1165,6 +1165,14 @@ reg = <0x021c>, <0x0220>; }; + optfclk_pciephy_32khz: optfclk_pciephy_32khz@4a0093b0 { + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + #clock-cells = <0>; + reg = <0x13b0>; + ti,bit-shift = <8>; + }; + optfclk_pciephy_div: optfclk_pciephy_div@4a00821c { compatible = "ti,divider-clock"; clocks = <&apll_pcie_ck>;
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