This patch fixes faulty behaviour in a setup where the input clock for
the SRG is fed through the CLKR pin but the McBSP is configured to be
master (SND_SOC_DAIFMT_CBS_CFS). In that case of course CLKR must not be
configured as output pin. Otherwise the input clock is messed up
horribly. The same reasoning applies if CLKX is configured as input for
the SRG.

Signed-off-by: Thomas Niederprüm <[email protected]>
---
 sound/soc/omap/omap-mcbsp.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c
index bd3ef2a..c89f562 100644
--- a/sound/soc/omap/omap-mcbsp.c
+++ b/sound/soc/omap/omap-mcbsp.c
@@ -530,8 +530,12 @@ static int omap_mcbsp_dai_set_dai_sysclk(struct 
snd_soc_dai *cpu_dai,
 
        case OMAP_MCBSP_SYSCLK_CLKX_EXT:
                regs->srgr2     |= CLKSM;
+               regs->pcr0      |= SCLKME;
+               regs->pcr0      &= ~CLKXM;
+               break;
        case OMAP_MCBSP_SYSCLK_CLKR_EXT:
                regs->pcr0      |= SCLKME;
+               regs->pcr0      &= ~CLKRM;
                break;
        default:
                err = -ENODEV;
-- 
2.1.1

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