On 10 November 2015 at 11:23, Delio Brignoli <dbrign...@audioscience.com> wrote: > are you aware of section 2.1.2 of ...
I am. It seems that the digital PLLs tend to produce an asymmetrical clock in general hence you need an even postdivider to get a 50% duty cycle. DPLL-S however already has an implicit /2 divider integrated, and a few peripherals seem to be fine with an asymmetrical clock (e.g. apparently the USB subsystem which is clocked by PLL_USB / 5). In the most recent SoCs they included a "DC corrector" in some PLLs to be able to symmetrize the clock without the need for postdivision. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
