The 3430SDPs, many of which use Qimonda SDRAM, are finally using bootloaders that program rounded rates for DPLL3. Since no SDRAM memory timings are defined for the rounded rates, the initial SDRC reprogram during init fails. Add in the correct timings here.
Problem reported by Kevin Hilman <[email protected]>. Signed-off-by: Paul Walmsley <[email protected]> Tested-by: Kevin Hilman <[email protected]> --- .../mach-omap2/sdram-qimonda-hyb18m512160af-6.h | 18 ++++++++++++++++-- 1 files changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h b/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h index 8b6f929..3751d29 100644 --- a/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h +++ b/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h @@ -19,20 +19,34 @@ /* Qimonda HYB18M512160AF-6 */ static struct omap_sdrc_params hyb18m512160af6_sdrc_params[] = { [0] = { - .rate = 165941176, + .rate = 166000000, .actim_ctrla = 0x629db4c6, .actim_ctrlb = 0x00012214, .rfr_ctrl = 0x0004dc01, .mr = 0x00000032, }, [1] = { + .rate = 165941176, + .actim_ctrla = 0x629db4c6, + .actim_ctrlb = 0x00012214, + .rfr_ctrl = 0x0004dc01, + .mr = 0x00000032, + }, + [2] = { + .rate = 83000000, + .actim_ctrla = 0x31512283, + .actim_ctrlb = 0x0001220a, + .rfr_ctrl = 0x00025501, + .mr = 0x00000022, + }, + [3] = { .rate = 82970588, .actim_ctrla = 0x31512283, .actim_ctrlb = 0x0001220a, .rfr_ctrl = 0x00025501, .mr = 0x00000022, }, - [2] = { + [4] = { .rate = 0 }, }; -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
