Rajendra Nayak <[email protected]> writes:

> The pwrdm_enable_hdwr_sar/pwrdm_disable_hdwr_sar do not
> actually set/reset the SAVEANDRESTORE bit in the PWSTCTRL
> register but modify some other bit instead.
> This happens due to the OMAP3430ES2_SAVEANDRESTORE_SHIFT
> being defined as (1 << 4) instead of just 4.
>
> Signed-off-by: Rajendra Nayak <[email protected]>

Thanks, pushing to PM branch.

I'll wait to hear from Kalle if we can revert his previous patch
for this.

Kevin

> ---
>  arch/arm/mach-omap2/prm-regbits-34xx.h |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h 
> b/arch/arm/mach-omap2/prm-regbits-34xx.h
> index 06fee29..d4ea370 100644
> --- a/arch/arm/mach-omap2/prm-regbits-34xx.h
> +++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
> @@ -411,7 +411,7 @@
>  /* PM_PREPWSTST_CAM specific bits */
>  
>  /* PM_PWSTCTRL_USBHOST specific bits */
> -#define OMAP3430ES2_SAVEANDRESTORE_SHIFT             (1 << 4)
> +#define OMAP3430ES2_SAVEANDRESTORE_SHIFT             4
>  
>  /* RM_RSTST_PER specific bits */
>  
> -- 
> 1.5.4.7
>
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