This patch fixes a bug in the CORE dpll scaling sequence
which was errouneously clearing some bits in the
SDRC DLLA CTRL register and hence causing a freeze.
The issue was observed only on platforms which scale
CORE dpll to < 83Mhz and hence program the DLL in fixed 
delay mode.

Signed-off-by: Rajendra Nayak <[email protected]>
---
 arch/arm/mach-omap2/sram34xx.S |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 481f912..9be09a7 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -113,7 +113,7 @@ return_to_sdram:
 unlock_dll:
        ldr     r11, omap3_sdrc_dlla_ctrl
        ldr     r12, [r11]
-       and     r12, r12, #FIXEDDELAY_MASK
+       bic     r12, r12, #FIXEDDELAY_MASK
        orr     r12, r12, #FIXEDDELAY_DEFAULT
        orr     r12, r12, #DLLIDLE_MASK
        str     r12, [r11]              @ (no OCP barrier needed)
-- 
1.5.4.7

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