Hi, From: "Palande Ameya (Nokia-D/Helsinki)" <[email protected]> Subject: [PATCH 10/13] DSPBRIDGE: HACK: insert delay for DPLL stabilization Date: Wed, 15 Jul 2009 16:56:33 +0200
> *HACK*: status register should be checked for this purpose. > > [Hiroshi DOYU: split the original to logical ones] > > Signed-off-by: Ameya Palande <[email protected]> > Acked-by: Omar Ramirez Luna <[email protected]> > --- > drivers/dsp/bridge/wmd/tiomap_sm.c | 7 +++++++ > 1 files changed, 7 insertions(+), 0 deletions(-) > > diff --git a/drivers/dsp/bridge/wmd/tiomap_sm.c > b/drivers/dsp/bridge/wmd/tiomap_sm.c > index 7d389e3..02e2675 100644 > --- a/drivers/dsp/bridge/wmd/tiomap_sm.c > +++ b/drivers/dsp/bridge/wmd/tiomap_sm.c > @@ -141,6 +141,13 @@ DSP_STATUS CHNLSM_InterruptDSP2(struct WMD_DEV_CONTEXT > *pDevContext, > temp = (temp & 0xFFFFFF08) | 0x37; > *(REG_UWORD32 *)(resources.dwCmBase + 0x4) = temp; > > + /* > + * This delay is needed to avoid mailbox timed out > + * issue experienced while SmartReflex is ON. > + * TODO: Instead of 1 ms calculate proper value. > + */ > + mdelay(1); > + I have tried the following patch and it seems that CM_IDLEST_PLL_IVA2 has never got locked. Is any special sequence required? >From af2ab46ad5bdcae57e7bf9ac735e3862ec2f45e6 Mon Sep 17 00:00:00 2001 From: Hiroshi DOYU <[email protected]> Date: Thu, 16 Jul 2009 11:48:19 +0300 Subject: [PATCH 1/1] DSPBRIDGE: poll IDLEST_PLL register for DPLL locking From: Hiroshi DOYU <[email protected]> Signed-off-by: Hiroshi DOYU <[email protected]> --- drivers/dsp/bridge/wmd/tiomap_sm.c | 21 +++++++++++++++------ 1 files changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/dsp/bridge/wmd/tiomap_sm.c b/drivers/dsp/bridge/wmd/tiomap_sm.c index ca9202d..aaea896 100644 --- a/drivers/dsp/bridge/wmd/tiomap_sm.c +++ b/drivers/dsp/bridge/wmd/tiomap_sm.c @@ -137,12 +137,21 @@ DSP_STATUS CHNLSM_InterruptDSP2(struct WMD_DEV_CONTEXT *pDevContext, temp = (temp & 0xFFFFFF08) | 0x37; *(REG_UWORD32 *)(resources.dwCmBase + 0x4) = temp; - /* - * This delay is needed to avoid mailbox timed out - * issue experienced while SmartReflex is ON. - * TODO: Instead of 1 ms calculate proper value. - */ - mdelay(1); + /* Poll CM_IDLEST_PLL_IVA2 */ + timeout = jiffies + msecs_to_jiffies(1000); + while (1) { + u32 l; + + l = __raw_readl(resources.dwCmBase + 0x24); + if (l & 1) + break; + + if (time_after(jiffies, timeout)) { + pr_err("%s(): dpll2 lock timeout\n", __func__); + return WMD_E_TIMEOUT; + } + } + pr_info("%s(): dpll2 locked\n", __func__); /* Restore mailbox settings */ HW_MBOX_restoreSettings(resources.dwMboxBase); -- 1.6.0.4 > /* Restore mailbox settings */ > HW_MBOX_restoreSettings(resources.dwMboxBase); > > -- > 1.6.2.4 > -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
