On Thu, 30 Jul 2009 15:49:29 +0300
Eduardo Valentin <[email protected]> wrote:

> --- a/arch/arm/plat-omap/mcbsp.c
> +++ b/arch/arm/plat-omap/mcbsp.c
> @@ -394,7 +394,8 @@ void omap_mcbsp_start(unsigned int id)
>       w = OMAP_MCBSP_READ(io_base, SPCR1);
>       OMAP_MCBSP_WRITE(io_base, SPCR1, w | 1);
>  
> -     udelay(100);
> +     /*  Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec */
> +     udelay(500);
>  
Note: udelay(100) us used to wait at least 2 CLKSRG cycles (as stated
in TRM).

Are you sure this change is necessary? CLKSRG is kind of master clock
to McBSP so original stetson guessed (?) 100 us should be fine for all
serial links where bit clock is higher than 20 kHz.

-- 
Jarkko
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