Paul Walmsley <[email protected]> writes:

> On Thu, 26 Nov 2009, Thara Gopinath wrote:
>
>> MPU power domain bank 0 bits are displayed in position of bank 1
>> in PWRSTS and PREPWRSTS registers. So read them from correct
>> position
>> 
>> Signed-off-by: Thara Gopinath <[email protected]>
>> Cc: Kevin Hilman <[email protected]>

Signed-off-by: Kevin Hilman <[email protected]>

> Thanks Thara, will queue this up.

Kevin
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