On Mon, Dec 14, 2009 at 1:59 PM, Paul Walmsley <[email protected]> wrote:
> Hello John,
Hi Paul,
>
> On Mon, 14 Dec 2009, John Faith wrote:
>
>> I'm trying to enable the sys_clkout2 pin in a 2.6.29 kernel for my
>> 3530EVM-like board for the main clock line of an FPGA. I've added a
>> MUX_CFG_34XX entry in mux.c, set the gpio direction in my board.c
>> file, and set the rate in my driver with clk_set_parent(),
>> clk_set_rate() but I do not see any output clock when probed with a
>> scope.
>
> Sounds like either the clock is not enabled (use clk_enable() for this),
> or there is a mux problem.
>
> You might also want to make sure that you've set the parent of
> clkout2_src_ck appropriately, although you still should be able to get
> something out of it.
After 3 clk_get() for clkout2_src_ck, sys_clkout2, and func_96m_ck, I
set the parent the same as n810.c with:
clk_set_parent(sys_clkout2_src, func96m_clk);
clk_set_rate(sys_clkout2, 12000000);
Calling clk_enable(sys_clkout2); returns zero.
As a test, I also tried going around the clock APIs and enabling the
clock directly with by writing to the CM_CLKOUT_CTRL register, with
similar results (no output).
My mux setting is:
MUX_CFG_34XX("SYS_CLKOUT2", 0x1E2,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
Thanks for the suggestions!
,
John
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