On Mon, Jan 18, 2010 at 01:59:22 +0530, Vishwanath BS wrote: > In 3630, DPLL4M2 o/p can be 96MH or 192MHz (for SGX to run at 192). This > patch has changes to support this feature. 96MHz clock is generated by > dividing 192Mhz clock by 2 using CM_CLKSEL_CORE register. > SGX can select Core Clock, 192MHz clock or CM_96M_FCLK as it's > functional clock. In summary changes done are 1. Added a feature called > omap3_has_192mhz_clk and enabled for 3630 2. Added a new clock node > called omap_192m_alwon_ck 3. Made omap_96m_alwon_fck to derive it's > clock from omap_192m_alwon_ck > > Cc: Paul Walmsley <[email protected]> > > Signed-off-by: Vishwanath BS <[email protected]> > --- > arch/arm/mach-omap2/clock34xx_data.c | 72 > ++++++++++++++++++++++++++++----- > arch/arm/mach-omap2/cm-regbits-34xx.h | 2 + > arch/arm/mach-omap2/id.c | 3 + > arch/arm/plat-omap/include/plat/cpu.h | 2 + > 4 files changed, 68 insertions(+), 11 deletions(-) > [snip]
> diff --git a/arch/arm/plat-omap/include/plat/cpu.h > b/arch/arm/plat-omap/include/plat/cpu.h > index 9a028bd..6718e40 100644 > --- a/arch/arm/plat-omap/include/plat/cpu.h > +++ b/arch/arm/plat-omap/include/plat/cpu.h > @@ -500,6 +500,7 @@ extern u32 omap3_features; > #define OMAP3_HAS_SGX BIT(2) > #define OMAP3_HAS_NEON BIT(3) > #define OMAP3_HAS_ISP BIT(4) > +#define OMAP3_HAS_192MHZ_CLK BIT(5) Looks like it could use a couple more tabs before "BIT(5)". Regards, -- Alex -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
