>From f9a7f877368830fdf28f9892940d05517f07a582 Mon Sep 17 00:00:00 2001 From: Mike Turquette <[email protected]> Date: Tue, 12 Jan 2010 16:58:39 +0530 Subject: [PATCH 1/2] OMAP3630: Clock: add clksel_shift to struct clk
Introduces clksel_shift to struct clk and populates the same for dpll4_m3_ck, dpll4_m4_ck, dpll4_m2_ck, dpll4_m6, dpll4_m5_ck and dpll3_m3. The purpose of this change is to make it easy for a generic function to refresh specific CM_CLKSEL registers on a per-clock basis by first adding then subtracting the shift value from the register.This is the recommended sequence to solve HSDivider PWRDN limitations in OMAP3630. Signed-off-by: Mike Turquette <[email protected]> Signed-off-by: Vijaykumar GN <[email protected]> --- arch/arm/mach-omap2/clock34xx_data.c | 6 ++++++ arch/arm/plat-omap/include/plat/clock.h | 1 + 2 files changed, 7 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock34xx_data.c index 6473247..ed17501 100755 --- a/arch/arm/mach-omap2/clock34xx_data.c +++ b/arch/arm/mach-omap2/clock34xx_data.c @@ -537,6 +537,7 @@ static struct clk dpll3_m3_ck = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_DIV_DPLL3_MASK, + .clksel_shift = OMAP3430_DIV_DPLL3_SHIFT, .clksel = div16_dpll3_clksel, .clkdm_name = "dpll3_clkdm", .recalc = &omap2_clksel_recalc, @@ -677,6 +678,7 @@ static struct clk dpll4_m2_ck_3630 __initdata = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), .clksel_mask = OMAP3630_DIV_96M_MASK, + .clksel_shift = OMAP3430_DIV_96M_SHIFT, .clksel = div32_dpll4_clksel, .clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, @@ -792,6 +794,7 @@ static struct clk dpll4_m3_ck_3630 __initdata = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), .clksel_mask = OMAP3630_CLKSEL_TV_MASK, + .clksel_shift = OMAP3430_CLKSEL_TV_SHIFT, .clksel = div32_dpll4_clksel, .clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, @@ -892,6 +895,7 @@ static struct clk dpll4_m4_ck_3630 __initdata = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), .clksel_mask = OMAP3630_CLKSEL_DSS1_MASK, + .clksel_shift = OMAP3430_CLKSEL_DSS1_SHIFT, .clksel = div32_dpll4_clksel, .clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, @@ -933,6 +937,7 @@ static struct clk dpll4_m5_ck_3630 __initdata = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), .clksel_mask = OMAP3630_CLKSEL_CAM_MASK, + .clksel_shift = OMAP3430_CLKSEL_CAM_SHIFT, .clksel = div32_dpll4_clksel, .clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, @@ -970,6 +975,7 @@ static struct clk dpll4_m6_ck_3630 __initdata = { .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3630_DIV_DPLL4_MASK, + .clksel_shift = OMAP3430_DIV_DPLL4_SHIFT, .clksel = div32_dpll4_clksel, .clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h index 71d78f7..e841755 100644 --- a/arch/arm/plat-omap/include/plat/clock.h +++ b/arch/arm/plat-omap/include/plat/clock.h @@ -93,6 +93,7 @@ struct clk { #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ defined(CONFIG_ARCH_OMAP4) u8 fixed_div; + u8 clksel_shift; void __iomem *clksel_reg; u32 clksel_mask; const struct clksel *clksel; -- 1.5.6.3 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
