Removes TWL4030 sleep script prior to rebooting, only on OMAP3. This is
necessary since DPLL3 reset causes SYS_OFFMODE pin to go low, resulting
in the sleep script being executed on TWL4030. This usually results in
VDD1 & VDD2 voltage collapse while ROM code is executing, followed by an
MPU Watch Dog reset or worse, an irrecoverable hang.
Signed-off-by: Mike Turquette <mturque...@ti.com>
---
arch/arm/mach-omap2/clock34xx.c | 15 +++++++++++++++
1 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 0d30e53..0d6d1d6 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -28,6 +28,7 @@
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/cpufreq.h>
+#include <linux/i2c/twl.h>
#include <plat/cpu.h>
#include <plat/clock.h>
@@ -311,6 +312,8 @@ struct clk_functions omap2_clk_functions = {
*/
void omap2_clk_prepare_for_reboot(void)
{
+ int err = 0;
+
/* REVISIT: Not ready for 343x */
#if 0
u32 rate;
@@ -321,6 +324,18 @@ void omap2_clk_prepare_for_reboot(void)
rate = clk_get_rate(sclk);
clk_set_rate(vclk, rate);
#endif
+
+ /*
+ * PRCM on OMAP3 will drive SYS_OFFMODE low during DPLL3 warm reset.
+ * This causes Gaia sleep script to execute, usually killing VDD1 and
+ * VDD2 while code is running. WA is to disable the sleep script
+ * before warm reset.
+ */
+#ifdef CONFIG_TWL4030_POWER
+ err = twl4030_remove_script(TWL4030_SLEEP_SCRIPT);
+ if (err)
+ pr_err("twl4030: error trying to disable sleep script!\n");
+#endif
}
void omap3_clk_lock_dpll5(void)
--
1.6.3.2
--
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