Add necessary clk_sel definitions to clock framework to allow changing
dpll4_m5_ck_3630 rate. This is used by the ISP driver.

Signed-off-by: Vimarsh Zutshi <[email protected]>
---
 arch/arm/mach-omap2/clock34xx_data.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/clock34xx_data.c 
b/arch/arm/mach-omap2/clock34xx_data.c
index f85e33a..8f15f18 100755
--- a/arch/arm/mach-omap2/clock34xx_data.c
+++ b/arch/arm/mach-omap2/clock34xx_data.c
@@ -937,6 +937,8 @@ static struct clk dpll4_m5_ck_3630 __initdata = {
        .clksel_shift   = OMAP3430_CLKSEL_CAM_SHIFT,
        .clksel         = div32_dpll4_clksel,
        .clkdm_name     = "dpll4_clkdm",
+       .set_rate       = &omap2_clksel_set_rate,
+       .round_rate     = &omap2_clksel_round_rate,
        .recalc         = &omap2_clksel_recalc,
 };
 
-- 
1.5.6.5

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